IDT72255LA15PFG IDT, Integrated Device Technology Inc, IDT72255LA15PFG Datasheet - Page 23

• Manufacturer Part Number: IDT72255LA15PFG
• Description: IC FIFO SUPERSYNC 8KX18 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA15PFG

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 15ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 72255LA15PFG; 800-1500

NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth.
2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
WCLK
WCLK
RCLK
RCLK
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
[
t
ENH
(2) ,
t
SKEW2
1
D/2 words in FIFO
(3)
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
+ 1
(4)
]
words in FIFO
t
t
D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.
CLKH
PAE
(1)
2
,
SKEW2
(2)
t
ENS
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
CLKL
23
t
ENH
t
ENS
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D/2 + 1 words in FIFO
t
ENH
+ 2
]
(2) ,
(3)
words in FIFO
t
HF
1
(1)
COMMERCIAL AND INDUSTRIAL
,
(2)
TEMPERATURE RANGES
t
PAE
[
PAE
D/2 words in FIFO
). If the time between
2
JANUARY 13, 2009
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4670 drw 21
4670 drw 20
(1)
,
(2)
(2) ,
(3)