IDT72255LA15PFG IDT, Integrated Device Technology Inc, IDT72255LA15PFG Datasheet - Page 17

IC FIFO SUPERSYNC 8KX18 64QFP

IDT72255LA15PFG

Manufacturer Part Number
IDT72255LA15PFG
Description
IC FIFO SUPERSYNC 8KX18 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT72255LA15PFG

Function
Synchronous
Memory Size
144K (8K x 18)
Access Time
15ns
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Other names
72255LA15PFG
800-1500

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72255LA15PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72255LA15PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72255LA15PFGI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Q
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
D
Q
NOTES:
1. t
2. LD = HIGH.
3. First word latency: 60ns + t
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
D
WCLK
RCLK
WCLK
0
0
0
0
RCLK
rising edge of the RCLK and the rising edge of the WCLK is less than t
WEN
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
- Q
- D
REN
SKEW3
- D
- Q
FF
n
n
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
t
OLZ
SKEW1
t
ENH
t
REF
t
REF
A
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
OE
(1)
+ 1*
TRCLK
t
t
SKEW3
ENH
t
ENS
t
DS
t
A
.
D
(1)
1
0
NO WRITE
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
t
t
DHS
ENH
LAST WORD
1
SKEW3
2
t
WFF
, then EF deassertion may be delayed one extra RCLK cycle.
SKEW1
t
t
DS
OHZ
t
t
DS
t
ENS
CLKH
, then the FF deassertion may be delayed one extra WCLK cycle.
D
D
1
X
NO OPERATION
t
WFF
t
t
17
ENH
DATA READ
DH
t
t
DH
CLK
2
t
CLKL
t
CLKH
t
t
REF
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
WFF
2
REF
TEMPERATURE RANGES
). If the time between the
). If the time between the
NEXT DATA READ
t
t
ENS
WFF
JANUARY 13, 2009
t
DS
D
0
D
X
+1
t
REF
t
t
4670 drw10
ENH
A
t
DH
t
WFF
4670 drw 11
D
1

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