TDF8599 NXP Semiconductors, TDF8599 Datasheet - Page 30

• Manufacturer Part Number: TDF8599
• Description: I2C-bus controlled dual channel 43 W/2 W single channel 85 W/1 W class-D power amplifier
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
Table 19.
V
[1]
[2]
[3]
[4]
[5]
[6]
TDF8599_1
Product data sheet
Symbol
t
Speaker load impedance
R
d
p
L
= 14.4 V; f
Required resistor accuracy for pins ADS and MOD is 1 %; see
Maximum leakage current from DCP pin to ground = 3 A.
DC output offset voltage is applied to the output during the transition between Mute mode and Operating mode in a gradual way.
I
The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.
The DC load valid bit DB1[D6] must be used;
detection cycle to prevent amplifier hang-up incidents.
2
C-bus mode only.
Static characteristics
osc
= 320 kHz; 40 C < T
Parameter
delay time
load resistance
…continued
amb
< +85 C; unless otherwise specified.
Section 8.6.2.1 on page
Rev. 01 — 13 November 2008
Conditions
shutdown delay time from EN pin
low to SVRR low; SVRR < 0.1 V;
C
shutdown delay time from pin EN
low to ACGND low; voltage on pin
ACGND < 0.1 V; Master mode
delay in Master mode to allow
slaved devices to shutdown
f
stereo mode
parallel mode
osc
SVR
= 320 kHz
Section 9 on page
= 47 F
19. The DC load enable bit IB2[D2] must be reset after each load
Class-D power amplifier with load diagnostics
23.
Min
145
-
-
1.6
0.8
TDF8599
© NXP B.V. 2008. All rights reserved.
Typ
260
400
50
4
-
Max
425
-
-
-
-
30 of 52
Unit
ms
ms
ms