74F163ASJX Fairchild Semiconductor, 74F163ASJX Datasheet - Page 3

• Manufacturer Part Number: 74F163ASJX
• Description: IC BINARY COUNTER SYNC 16SOP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F163ASJX

• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Synchronous
• Timing: Synchronous
• Count Rate: 120MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous
(74F163A), parallel load, count-up and hold. Five control
inputs—Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-
lel (CEP) and Count Enable Trickle (CET)—determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchro-
nously forces all outputs LOW. A LOW signal on SR over-
rides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (P
Mode Select Table
H
L
X
Note 1: For 74F163A only
Block Diagram
Functional Description
LOW Voltage Level
HIGH Voltage Level
Immaterial
(Note 1)
SR
L
H
H
H
H
n
) inputs to be loaded into the flip-flops on the next
PE CET
X
H
H
H
L
reset
H
X
X
L
X
(74F161A),
CE
P
X
X
H
X
L
Reset (Clear)
Load (P
Count (Increment)
No Change (Hold)
No Change (Hold)
Action on the Rising
Clock Edge (
synchronous
n
Q
n
)

)
reset
3
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchro-
nous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, counters or registers.
Logic Equations: Count Enable
State Diagram
TC
CEP • CET • PE
Q
0
• Q
www.fairchildsemi.com
1
• Q
2
• Q
3
• CET