DM74LS161AM Fairchild Semiconductor, DM74LS161AM Datasheet

DM74LS161AM

Manufacturer Part Number

DM74LS161AM

Description

IC COUNTER BINARY PRESET 16-SOIC

Manufacturer

Fairchild Semiconductor

Series

74LSr

Datasheet

1.DM74LS161AN.pdf (10 pages)

Specifications of DM74LS161AM

Logic Type

Binary Counter

Direction

Number Of Elements

Number Of Bits Per Element

Reset

Asynchronous

Timing

Synchronous

Trigger Type

Positive Edge

Voltage - Supply

4.75 V ~ 5.25 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

16-SOIC (3.9mm Width)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Count Rate

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DM74LS161AM

DM74LS161AN

DM74LS163AM

DM74LS163AN

DM74LS161A • DM74LS163A

Synchronous 4-Bit Binary Counters

General Description

These synchronous, presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs. The DM74LS161A and DM74LS163A are 4-bit

binary counters. The carry output is decoded by means of

a NOR gate, thus preventing spikes during the normal

counting mode of operation. Synchronous operation is pro-

vided by having all flip-flops clocked simultaneously so that

the outputs change coincident with each other when so

instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting

spikes which are normally associated with asynchronous

(ripple clock) counters. A buffered clock input triggers the

four flip-flops on the rising (positive-going) edge of the

clock input waveform.

These counters are fully programmable; that is, the outputs

may be preset to either level. As presetting is synchronous,

setting up a low level at the load input disables the counter

and causes the outputs to agree with the setup data after

the next clock pulse, regardless of the levels of the enable

input. The clear function for the DM74LS161A is asynchro-

nous; and a low level at the clear input sets all four of the

flip-flop outputs LOW, regardless of the levels of clock,

load, or enable inputs. The clear function for the

DM74LS163A is synchronous; and a low level at the clear

inputs sets all four of the flip-flop outputs LOW after the

next clock pulse, regardless of the levels of the enable

inputs. This synchronous clear allows the count length to

be modified easily, as decoding the maximum count

desired can be accomplished with one external NAND

gate. The gate output is connected to the clear input to

synchronously clear the counter to all low outputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006397

The carry look-ahead circuitry provides for cascading

counters for n-bit synchronous applications without addi-

tional gating. Instrumental in accomplishing this function

are two count-enable inputs and a ripple carry output.

Both count-enable inputs (P and T) must be HIGH to count,

and input T is fed forward to enable the ripple carry output.

The ripple carry output thus enabled will produce a high-

level output pulse with a duration approximately equal to

the high-level portion of the Q

flow ripple carry pulse can be used to enable successive

cascaded stages. HIGH-to-LOW level transitions at the

enable P or T inputs may occur, regardless of the logic

level of the clock.

These counters feature a fully independent clock circuit.

Changes made to control inputs (enable P or T or load) that

will modify the operating mode have no effect until clocking

occurs. The function of the counter (whether enabled, dis-

abled, loading, or counting) will be dictated solely by the

conditions meeting the stable set-up and hold times.

Features

Synchronously programmable

Internal look-ahead for fast counting

Carry output for n-bit cascading

Synchronous counting

Load control line

Diode-clamped inputs

Typical propagation time, clock to Q output 14 ns

Typical clock frequency 32 MHz

Typical power dissipation 93 mW

Package Description

output. This high-level over-

August 1986

Revised April 2000

www.fairchildsemi.com

Related parts for DM74LS161AM

DM74LS161AM Summary of contents

Page 1

... The gate output is connected to the clear input to synchronously clear the counter to all low outputs. Ordering Code: Order Number Package Number DM74LS161AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide ...

Page 2

Connection Diagram Logic Diagram The DM74LS161A is similar, however, the clear buffer is connected directly to the flip-flops. www.fairchildsemi.com DM74LS163A 2 ...

Page 3

Parameter Measurement Information The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50 OUT R Vary PRR to measure f . MAX Outputs Q and carry are tested at ...

Page 4

Timing Diagram LS161A, LS163A Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one, and two (4) Inhibit www.fairchildsemi.com 4 ...

Page 5

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range DM74LS161A Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level ...

Page 6

DM74LS161A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage HIGH Level V OH Output Voltage V V LOW Level V OL Output Voltage Input ...

Page 7

DM74LS163A Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output Current OH I LOW Level Output Current OL f Clock Frequency (Note 8) CLK ...

Page 8

DM74LS163A Switching Characteristics and Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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