IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 9

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
17
17
15
15
14
14
IDT72275 (32,768 x 18  BIT)
LD
0
0
0
X
1
1
1
EMPTY OFFSET REGISTER
03FFH if LD is HIGH at Master Reset
FULL OFFSET REGISTER
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
WEN
DEFAULT VALUE
X
DEFAULT VALUE
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
SEN
Figure 3. Offset Register Location and Default Values
1
1
X
X
X
1
0
WCLK
X
X
X
X
0
0
RCLK
9
X
X
X
X
X
17
17
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
30 bits for the IDT72275
32 bits for the IDT72285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
16
16
IDT72285 (65,536 x 18  BIT)
15
15
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
IDT72275
IDT72285
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
4674 drw07
4674 drw06
0
0