IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 20

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit
3. OE = LOW
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
NOTE:
1. X = 14 for the IDT72275 and X = 15 for the IDT72285.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
Q
WCLK
WCLK
RCLK
0
setup procedure. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
WEN
SEN
REN
- Q
PAE
PAF
1
LD
OR
, W
HF
RT
SI
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
t
ENS
LDS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
ENH
LDH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
Figure 12. Retransmit Timing (FWFT Mode)
SKEW2
1
2
t
PAF
1
W
x+1
BIT X
20
(1)
BIT 0
2
t
PAE
FULL OFFSET
COMMERCIAL AND INDUSTRIAL
3
t
A
t
t
ENH
REF
(5)
TEMPERATURE RANGES
W
1
(4)
BIT X
t
t
t
LDH
LDH
t
ENH
DH
(1)
W
4
t
2
4674 drw 16
A
4674 drw 15
t
ENH
W
3