IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 16

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

Q
D
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
Q
NOTES:
1. t
2. LD = HIGH
D
WCLK
WCLK
0
0
RCLK
RCLK
0
0
WEN
between the rising edge of the RCLK and the rising edge of the WCLK is less than t
WEN
REN
SKEW1
REN
the rising edge of WCLK and the rising edge of RCLK is less than t
- D
- Q
- Q
- D
SKEW3
FF
OE
EF
n
n
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
SKEW1
t
OLZ
t
ENH
t
REF
t
A
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
OE
(1)
t
t
ENH
SKEW3
t
ENS
t
t
A
DS
D
1
(1)
0
NO WRITE
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
t
t
DHS
ENH
LAST WORD
1
2
t
WFF
t
SKEW3
DS
t
OHZ
t
t
t
DS
CLKH
ENS
, then EF deassertion may be delayed one extra RCLK cycle.
D
D
1
X
NO OPERATION
t
WFF
t
t
16
DATA READ
ENH
DH
SKEW1
t
DH
t
CLK
2
, then the FF deassertion may be delayed one extra WCLK cycle.
t
CLKL
t
CLKH
t
t
ENS
REF
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
COMMERCIAL AND INDUSTRIAL
A
2
TEMPERATURE RANGES
WFF
NEXT DATA READ
t
REF
t
ENS
WFF
). If the time
t
DS
). If the time between
D
0
D
X
+1
t
REF
t
t
4674 drw10
ENH
A
t
DH
t
WFF
4674 drw 11
D
1