IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 22

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
WCLK
RCLK
WCLK
RCLK
WEN
REN
between the rising edge of WCLK and the rising edge of RCLK is less than t
WEN
PAE
SKEW2
REN
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
n words in FIFO
n+1 words in FIFO
ENS
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
(2)
t
ENH
t
[
,
SKEW2
(3)
D-1
1
2
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
D/2 words in FIFO
+ 1
(4)
]
words in FIFO
t
t
CLKH
PAE
(1)
,
2
(2)
t
ENS
t
CLKL
SKEW2
, then the PAE deassertion may be delayed one extra RCLK cycle.
22
t
ENH
t
t
ENS
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
2
t
ENH
+ 2
]
words in FIFO
(2)
(3)
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
t
[
PAE
D-1
TEMPERATURE RANGES
2
D/2 words in FIFO
+ 1
2
PAE
]
words in FIFO
). If the time
n words in FIFO
n+1 words in FIFO
4674 drw 21
(1)
4674 drw 20
,
(2)
(2)
,
(3)