IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 23

no-image

IDT72285

Manufacturer Part Number
IDT72285
Description
64k X 18 Supersync Fifo, 5.0v
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72285L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72285L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72285L10PFG
Manufacturer:
M/A-COM
Quantity:
1 450
Part Number:
IDT72285L10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72285L10TF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72285L10TF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72275
72285
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
23
0
n
- Qm
problems can be avoided by creating composite flags, that is, ANDing EF of
every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
devices. D
from each device form a 36-bit wide output bus. Any word width can be attained
by adding additional IDT72275/72285 devices.
Figure 23 demonstrates a width expansion using two IDT72275/72285
72275
72285
FIFO
IDT
#2
0
- D
17
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAE)
from each device form a 36-bit wide input bus and Q
Qm
+1
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
4674 drw 22
GATE
(1)
0
-Q
17

Related parts for IDT72285