GS1503B Gennum Corporation, GS1503B Datasheet - Page 73

• Manufacturer Part Number: GS1503B
• Description: Hd Embedded Audio Codec
• Manufacturer: Gennum Corporation

Table 5-27: Register Settings
5.11 Demultiplex Mode With Word Clock Input
Name
ANCI
DEL_SEL
ADPG4_DEL
ADPG3_DEL
ADPG2_DEL
ADPG1_DEL
ACPG4_DEL
ACPG3_DEL
ACPG2_DEL
ACPG1_DEL
NDID[7:0]
Description
Ancillary data packet delete (1: Deletion enabled)
Ancillary data packet delete mode select
(0: Entire data delete; 1: Group designated data delete)
Audio group 4 data packet delete (1: Delete)
Audio group 3 data packet delete (1: Delete)
Audio group 2 data packet delete (1: Delete)
Audio group 1 data packet delete (1: Delete)
Audio group 4 control packet delete (1: Delete)
Audio group 3 control packet delete (1: Delete)
Audio group 2 control packet delete (1: Delete)
Audio group 1 control packet delete (1: Delete)
Arbitrary packet DID delete setting
Some commercially available HD audio embedding modules do not encode the
audio word clock phase information correctly in the CLK words of the audio data
packet. If this clock information is not correctly encoded, the GS1503B will not
output the audio data correctly. Also, the GS1503B will be unable to reproduce the
48kHz audio word clock (fs) at the WCOUTA and WCOUTB pins in serial audio
output modes.
If the GS1503B is to be used in conjunction with a HD audio module, which
encodes audio clock phase information incorrectly, the DEC_MODE external pin
or DECMODE bit 2 of Host Interface register 01Eh must be set HIGH. When HIGH,
an audio word clock synchronous to the original word clock used for embedding
must be input at the WCINA and WCINB pins.
example.
When the embedded clock phase data for audio channel 1 to 4 is detected as being
in error, the MUXERRA bit 0 of Host Interface register 01Eh will be set HIGH.
Similarly, when the embedded clock phase data for audio channel 5 to 8 is
detected as being in error, the MUXERRB bit 1 of Host Interface register 01Eh will
be set HIGH.
Proprietary and Confidential
37953 - 0
Address
040
040
041
041
041
041
041
041
041
041
042
August 2006
Figure 5-13
Bit
7-0
1
0
7
6
5
4
3
2
1
0
GS1503B Data Sheet
shows a system
Setting
1
1
–
–
–
–
–
–
–
–
–
Default
73 of 88
0
0
0
0
0
0
0
0
0
0
0