GS1503B Gennum Corporation, GS1503B Datasheet - Page 31

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GS1503B

Manufacturer Part Number
GS1503B
Description
Hd Embedded Audio Codec
Manufacturer
Gennum Corporation
Datasheet
4.6.3 Audio Clock Phase Locked Loop
4.6.4 Audio Signal Input Detection
Y/C b / C r [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
Figure 4-14
AES/EBU audio input mode. The GS1503B will internally synchronize the
AES/EBU audio input to the corresponding ACLK, using the clock extracted from
the AES/EBU bi-phase mark encoding. This configuration is not required for serial
audio input modes.
Figure 4-14: Block Diagram of GS1503B Audio Clock PLL
The audio input signal detect registers will be set HIGH in AES/EBU audio mode
when the preamble of the audio input data is detected 3 times consecutively. In
serial audio input mode, the GS1503B will set the audio input signal detect
registers HIGH when a 48kHz word clock is detected at the corresponding inputs.
Audio channels 1 to 4 will be set when WCINA is validated, and audio channels 5
to 8 when WCINB is validated. Host Interface register 010h, bits 6-3, report the
individual audio channels pairs detected.
Proprietary and Confidential
VIN[19:0]
AIN1/2
AIN3/4
ACLKA
AIN5/6
AIN7/8
ACLKB
shows the configuration for deriving the 6.144MHz audio clock in
GS1503B
PLLCNTA
PLLCNTB
37953 - 0
6.144MHz (128 fs)
6.144MHz (128 fs)
Pass
Filter
Pass
Filter
Low
Low
August 2006
24.576MHz
24.576MHz
GS1503B Data Sheet
VCXO
VCXO
÷ 4
÷ 4
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