GS1503B Gennum Corporation, GS1503B Datasheet - Page 60

• Manufacturer Part Number: GS1503B
• Description: Hd Embedded Audio Codec
• Manufacturer: Gennum Corporation

5.6.2 Digital Audio Output Timing
5.6.2.1 AES/EBU Format Output
WCOUTA/WCOUTB
(AES/EBU)
MODE0
MODE1
MODE2
23
MSB
0
Preamble
Sync
3 4
LSB
0
Figure 5-6: Audio Output Formats
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB
inputs. ACLKA is used to clock AES/EBU digital audio signal for channels 1 to 4
(AOUT1/2 and AOUT3/4). ACLKB is used to clock AES/EBU digital audio signal for
channels 5 to 8 (AOUT5/6 and AOUT7/8). In AES/EBU output mode, the audio
word clock inputs WCINB and WCINB should be grounded. See
timing.
The user can access the Audio Channel Status Block information via the
AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio
Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh
should be set HIGH. The embedded audio channel from which the Channel Status
information is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface
register 06Fh. The CH_SEL[2:0] setting for audio channel 1 is 000b, through to
111b for channel 8. The CS_RQST bit must be set HIGH to begin the process of
extracting the Audio Channel Status information. Once extracted, the GS1503B
will set CS_WEND bit HIGH and the user can access the data for Host Interface
registers 058h to 06Eh.
When CS_MODE is set LOW, the Audio Channel Status information in the
AES/EBU audio outputs will be replaced with data programmed in the
AUDIO_CS[183:0] bits of Host Interface registers 058h to 06Eh.
Proprietary and Confidential
24-bit Audio Sample Word
Channel 1
Channel Status Bit
User Data Bit
Validity Bit
Parity Bit
0
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37953 - 0
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23
MSB
0
Preamble
Sync
3 4
August 2006
LSB
0
24-bit Audio Sample Word
GS1503B Data Sheet
Channel 2
Figure 5-7
0
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