ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 26

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

The writing of the AC RMS Power Threshold is different
than other SPI registers, and these registers are not
listed in the SPI memory map table. The required
algorithm is documented below.
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are
MSB-aligned to 12-bit data). A dynamic number of these
24-bit results are averaged to compare with this
threshold approximately every 1
not to freeze I2E. The 24-bit threshold is constructed
with bits 23 through 20 (MSBs) assigned to 0, bits 19
through 4 assigned to this 16-bit quantity, and bits 3
through 0 (LSBs) assigned to 0. The calculation
methodology to set this register is identical to the
description in the RMS power threshold description.
The freezing of I2E when the AC RMS power meter
threshold is not met affects the sample time skew
interleave mismatch estimate, but not the offset or gain
mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating
between the Hold and Track state, there is hysteresis
in the comparison described above. After I2E enters a
frozen state, the AC RMS input power must achieve ≥
threshold value + hysteresis to again enter the Track
state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being
assigned to 0, bits 11 through 4 assigned to this
register’s value, and bits 3 through 0 (LSBs) assigned
to 0.
ADDRESS 0X60-0X64: I2E INITIALIZATION
These registers provide access to the initialization values
for each of offset, gain, and sample time skew that I2E
programs into the target core A/D before adjusting to
minimize interleave mismatch. They can be used by the
system to, for example, reduce the convergence time of
the I2E algorithm by programming in the optimal values
before turning I2E on. In this case, I2E only needs to
adjust for temperature and voltage-induced changes
since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing
skew between the two A/D cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
1. Write the value 0x80 to the Index Register (SPI
2. Write the MSBs of the 16-bit quantity to SPI Address
3. Write the LSBs of the 16-bit quantity to SPI Address
address 0x10)
0x150
0x14F
26
µ
s to decide whether or
ISLA112P50
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple A/Ds are used in a time-interleaved system. The
phase slip feature allows the rising edge of the divided
clock to be advanced by one input clock cycle when in
CLK/2 mode, as shown in Figure 45. Execution of a
phase_slip command is accomplished by first writing a ‘0’
to bit 0 at address 71h followed by writing a ‘1’ to bit 0 at
address 71h (32 sclk cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA112P50 has a selectable clock divider that can
be set to divide by two or one (no division). By default,
the tri-level CLKDIV pin selects the divisor (refer to
“Clock Input” on page 16). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12. This register is not changed by a Soft Reset.
FIGURE 45. PHASE SLIP: CLK÷2 MODE,
A/D 0 CLOCK
A/D 1 CLOCK
A/D 0 CLOCK
A/D 1 CLOCK
A/D 0 CLOCK
A/D 1 CLOCK
SLIP TWICE
SLIP TWICE
SLIP ONCE
SLIP ONCE
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
CLK
–Full Scale (0x00)
+Full Scale (0xFF)
Nominal Step Size
Mid–Scale (0x80)
CLK
PARAMETER
÷
2
Steps
f
CLOCK
= 1000MHz
CLK = CLKP - CLKN
2.00ns
1.00ns
DIFFERENTIAL SKEW
4.00ns
0x70[7:0]
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+6.5ps
-6.5ps
0.0ps
51fs
256
March 30, 2010
FN7604.0