ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 25

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

Bit 5: 0 = bypass notch filter, 1 = use notch filter on
incoming data before estimating interleave mismatch
terms
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must
be written prior to turning I2E on for the settings to take
effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment
of the offset, gain, and sample time skew analog controls
when I2E is first turned on. This bit would typically be
used if optimal analog adjustment values for offset, gain,
and sample time skew have been preloaded in order to
have the I2E algorithm converge more quickly.
The system gain of the pair of interleaved core A/Ds can
be set by programming the medium and fine gain of the
reference A/D before turning I2E on. In this case, I2E will
adjust the non-reference A/D’s gain to match the
reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power
down the I2E algorithm and the Notch filter. This would
typically be done to conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch Filter
ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to
configure I2E’s dynamic freeze control. As with any
interleave mismatch correction algorithm making
estimates of the interleave mismatch errors using the
digitized application input signal, there are certain
characteristics of the input signal that can obscure the
mismatch estimates. For example, a DC input to the A/D
contains no information about the sample time skew
mismatch between the core A/Ds, and thus should not be
used by the I2E algorithm to update its sample time
skew estimate. Under such circumstances, I2E enters
Hold state. In the Hold state, the analog adjustments will
be frozen and mismatch estimate calculations will cease
until such time as the analog input achieves sufficient
quality to allow the I2E algorithm to make mismatch
estimates again.
These registers allow the programming of the thresholds
of the meters used to determine the quality of the input
signal. This can be used by the application to optimize
I2E’s behavior based on knowledge of the input signal.
For example, if a specific application had an input signal
that was typically 30dB down from full scale, and was
primarily concerned about analog performance of the
A/D at this input power, lowering the RMS power
threshold would allow I2E to continue tracking with this
input power level, thus allowing it to track over voltage
and temperature changes.
25
ISLA112P50
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
This 16-bit quantity is the RMS power threshold at which
I2E will enter Hold state. The RMS power of the analog
input is calculated continuously by I2E on incoming data.
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are MSB-
aligned to 12-bit data). A dynamic number of these 24-
bit results are averaged to compare with this threshold
approximately every 1
freeze I2E. The 24-bit threshold is constructed with bits
23 through 20 (MSBs) assigned to 0, bits 19 through 4
assigned to this 16-bit quantity, and bits 3 through 0
(LSBs) assigned to 0. As an example, if the application
wanted to set this threshold to trigger near the RMS
analog input of a -20dBFS sinusoidal input, the
calculation to determine this register’s value would be
RMS
hex 290
Therefore, programming 0x1488 into these two registers
will cause I2E to freeze when the signal being digitized
has less RMS power than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E
to freeze when the input amplitude is less than -21.2
dBFS.
The freezing of I2E by the RMS power meter threshold
affects the gain and sample time skew interleave
mismatch estimates, but not the offset mismatch
estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating
between the Hold and Track state, there is hysteresis
in the comparison described above. After I2E enters a
frozen state, the RMS input power must achieve ≥
threshold value + hysteresis to again enter the Track
state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being
assigned to 0, bits 11 through 4 assigned to this
register’s value, and bits 3 through 0 (LSBs) assigned
to 0.
AC RMS Power Threshold
Similar to RMS power threshold, there must be sufficient
AC RMS power (or dV/dt) of the input signal to measure
sample time skew mismatch for an arbitrary input. This is
clear from observing the effect when a high voltage (and
therefore large RMS value) DC input is applied to the A/D
input. Without sufficient dV/dt in the input signal, no
information about the sample time skew between the
core A/Ds can be determined from the digitized samples.
The AC RMS Power Meter is implemented as a high-
passed (via DSP) RMS power meter.
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0x014884
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March 30, 2010
0x1488
FN7604.0
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