ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 2

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

Table of Contents
Pin Descriptions ................................................ 4
Absolute Maximum Ratings .............................. 5
Thermal Information ........................................ 5
Recommended Operating Conditions ................ 5
Digital Specifications ........................................ 8
Timing Diagrams ............................................... 8
Switching Specifications .................................... 9
Typical Performance Curves ............................ 10
Theory of Operation......................................... 14
I2E Requirements and Restrictions ................. 19
Functional Description..................................... 14
Power-On Calibration ...................................... 14
User Initiated Reset........................................ 15
Analog Input ................................................. 15
Clock Input ................................................... 16
Jitter ............................................................ 16
Voltage Reference .......................................... 17
Digital Outputs .............................................. 17
Over Range Indicator...................................... 17
Power Dissipation........................................... 17
Nap/Sleep ..................................................... 17
Data Format .................................................. 18
Overview........................................................ 19
Active Run State ............................................ 19
Power Meter .................................................. 19
FS/4 Filter..................................................... 19
Nyquist Zones ............................................... 19
Configurability and Communication................... 20
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ISLA112P50
Clock Divider Synchronous Reset .................... 20
Serial Peripheral Interface .............................. 22
Equivalent Circuits .......................................... 31
A/D Evaluation Platform ................................. 33
Layout Considerations..................................... 33
Definitions....................................................... 33
Revision History.................................................. 34
Products.......................................................... 34
Package Outline Drawing ............................... 35
SPI Physical Interface .................................... 22
SPI Configuration .......................................... 23
Device Information ........................................ 23
Indexed Device Configuration/Control .............. 23
AC RMS Power Threshold ................................ 25
Address 0x60-0x64: I2E initialization ............... 26
Device Test................................................... 27
SPI Memory Map ........................................... 29
Split Ground and Power Planes ........................ 33
Clock Input Considerations ............................. 33
Exposed Paddle ............................................. 33
Bypass and Filtering....................................... 33
LVDS Outputs ............................................... 33
LVCMOS Outputs ........................................... 33
Unused Inputs .............................................. 33
L72.10x10C ................................................... 35
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March 30, 2010
FN7604.0