ISLA112P50 Intersil, ISLA112P50 Datasheet - Page 24

• Manufacturer Part Number: ISLA112P50
• Description: 500MSPS A/D Converter
• Manufacturer: Intersil

The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the A/D core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit. Multiple Coarse Gain Bits
can be set for a total adjustment range of ±4.2%.
(‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%) It is
recommended to use one of the coarse gain settings
(-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and
fine-tune the gain using the registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
+Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV)
+Full Scale (0xFF)
–Full Scale (0x00)
Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV)
–Full Scale (0x00)
Nominal Step Size
Mid–Scale (0x80)
Mid–Scale (0x80)
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
PARAMETER
0x22[3:0]
Steps
Steps
Bit3
Bit2
Bit1
Bit0
TABLE 8. COARSE GAIN ADJUSTMENT
TABLE 7. OFFSET ADJUSTMENTS
COARSE OFFSET
-133LSB (-47mV)
0.0LSB (0.0mV)
NOMINAL COARSE GAIN ADJUST
MEDIUM GAIN
0x20[7:0]
0x23[7:0]
0.016%
0.00%
24
+2%
255
-2%
256
(%)
+2.8
+1.4
-2.8
-1.4
-5LSB (-1.75mV)
FINE OFFSET
0x21[7:0]
FINE GAIN
0x24[7:0]
0.0016%
0.0LSB
-0.20%
+0.2%
0.00%
255
256
ISLA112P50
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 17). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or
Hold state. The state of the I2E circuitry is dependent on
the analog input signal itself. If the input signal obscures
the interleave mismatched artifacts such that I2E cannot
estimate the mismatch, the algorithm will dynamically
enter the Hold state. For example, a DC mid-scale input
to the A/D does not contain sufficient information to
estimate the gain and sample time skew mismatches,
and thus the I2E algorithm will enter the Hold state. In
the Hold state, the analog adjustments for interleave
correction will be frozen and mismatch estimate
calculations will cease until such time as the analog input
achieves sufficient quality to allow the I2E algorithm to
make mismatch estimates again.
Bit 0: 0 = I2E has not detected a low power condition.
1 = I2E has detected a low power condition, and the
analog adjustments for interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power
condition. 1 = I2E has detected a low AC power
condition, and I2E will continue to correct with best
known information but will not update its interleave
correction adjustments until the input signal achieves
sufficient AC RMS power.
Bit 2: When first started, the I2E algorithm can take a
significant amount of time to settle (~1s), dependent on
the characteristics of the analog input signal. 0 = I2E is
still settling, 1 = I2E has completed settling.
ADDRESS 0X31: I2E CONTROL
The I2E general control register. This register can be
written while I2E is running to control various
parameters.
Bit 0: 0 = turn I2E off, 1= turn I2E on
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings
in the current state. Subsequently writing a 0 to this bit
will allow I2E to continue from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of
offset, gain, or sample time skew
TABLE 10. POWER-DOWN CONTROL
VALUE
000
001
010
100
POWER DOWN MODE
Normal Operation
0x25[2:0]
Sleep Mode
Pin Control
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Nap Mode
March 30, 2010
FN7604.0