ISL6556A Intersil Corporation, ISL6556A Datasheet - Page 8

• Manufacturer Part Number: ISL6556A
• Description: Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application
• Manufacturer: Intersil Corporation

ENLL
This pin is implemented in QFN ISL6556A only. It’s a logic-
level enable input for the controller. When asserted to a logic
high, the ISL6556A is active depending on status of EN, the
internal POR, VID inputs and pending fault states.
Deasserting ENLL will clear all fault states and prime the
ISL6556A to soft start when re-enabled.
FS
A resistor, placed from FS to ground will set the switching
frequency. There is an inverse relationship between the
value of the resistor and the switching frequency. See Figure
13 and Equation 26.
VID4, VID3, VID2, VID1, VID0, and VID12.5
These are the inputs to the internal DAC that provides the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active-pull-up outputs. VID4-VID12.5 have
20 A internal pull-up current sources that diminish to zero as
the voltage rises above the logic-high level. These inputs
can be pulled up as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND
VSEN and RGND form the precision differential remote-
sense amplifier. This amplifier converts the differential
voltage of the remote output to a single-ended voltage
referenced to local ground. VDIFF is the amplifier’s output
and the input to the regulation and protection circuitry.
Connect VSEN and RGND to the sense pins of the remote
load.
FB and COMP
Inverting input and output of the error amplifier respectively.
FB is connected to VDIFF through a resistor. A negative
current, proportional to output current is present on the FB
pin. A properly sized resistor between VDIFF and FB sets
the load line (droop). The droop scale factor is set by the
ratio of the ISEN resistors and the lower MOSFET r
COMP is tied back to FB through an external R-C network to
compensate the regulator.
DAC and REF
The DAC output pin is the output of the precision internal
DAC reference. The REF input pin is the positive input of
the error amplifier. In typical applications, a 1k , 1%
resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID™ operations.
PWM1, PWM2, PWM3, PWM4
Pulse-width modulation outputs. Connect these pins to the
PWM input pins of the Intersil driver IC. The number of
active channels is determined by the state of PWM3 and
8
DS(ON)
ISL6556A
.
PWM4. Tie PWM3 to VCC to configure for 2-phase
operation. Tie PWM4 to VCC to configure for 3-phase
operation.
ISEN1, ISEN2, ISEN3, ISEN4
Current sense inputs. The ISEN1, ISEN2, ISEN3, and
ISEN4 pins are held to a virtual ground such that a resistor
connected between them and the drain terminal of the
associated lower MOSFET will carry a current proportional
to the current flowing through the related channel. The
current is determined by the negative voltage developed
across the lower MOSFET’s r
current scaled by the inverse of the r
used as a reference for channel balancing, protection, and
load-line regulation (via the FB pin). Inactive channels
should have their respective current sense inputs left open.
PGOOD
PGOOD is used as an indication of the end of soft-start per
the microprocessor specification. It is an open-drain logic
output that is low impedance until the soft start is
completed. It will be pulled low again once the under-voltage
point is reached.
OFS
The OFS pin provides a means to program a dc current for
generating a offset voltage at the REF input. The offset
current is generated via an external resistor and precision
internal voltage references. The polarity of the offset is
selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unterminated.
OFSOUT (ISL6556ACR only)
OFSOUT is the output of the offset-current generating
circuit. It must be connected either to REF (recommended)
or FB to generate a dc offset.
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
this pin to the gate of an SCR or MOSFET tied from V
V
be pulled as high as 15V to ground with an external resistor.
However, it is only capable of pulling low when VCC is
above 2V.
OUT
to ground to prevent damage to the load. This pin may
DS(ON)
DS(ON)
which is the channel
. The current is
IN
or