ISL6556A Intersil Corporation, ISL6556A Datasheet - Page 14

• Manufacturer Part Number: ISL6556A
• Description: Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application
• Manufacturer: Intersil Corporation

Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6556A checks the VID inputs six times every
switching cycle. If the VID code is found to have has
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between DAC level and the new VID
code changes sign no change is made. If the VID code is
more than 1 bit higher or lower than the DAC (not
recommended), the controller will execute 12.5mV changes
six times per cycle until VID and DAC are equal. It is for this
reason that it is important to carefully control the rate of VID
stepping in 1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R
based voltage regulator. The selection of R
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T
R
Typically R
change rate of 5 s per bit, the value of C
on Equation 9.
Initialization
Prior to initialization, proper conditions must exist on the
enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within
the proper window of operation, PGOOD asserts logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6556A
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
C
REF
REF
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6556A is guaranteed. Hysteresis between the
and C
R
REF
VID
REF
REF
=
, the relationship between the time constant of
REF
4 T
is selected to be 1k , so with a VID step
network and T
VID
and C
REF
14
is required for an ISL6556A
VID
REF
is given by Equation 9.
is based on the time
REF
REF
is 22nF based
is based on
(EQ. 9)
ISL6556A
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.24V; for
ISL6556ACR, ENLL must be logic high; and VID cannot be
equal to 111111 or 111110. When each of these conditions
is true, the controller immediately begins the soft-start
sequence.
2. The ISL6556A features an enable input (EN) for power
3. (ISL6556ACR only) The voltage on ENLL must be logic
4. The VID code must not be 111111 or 111110. These
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
rising and falling thresholds assure that once enabled,
the ISL6556A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6556A in shutdown until the voltage at EN rises above
1.24V. The enable comparator has about 90mV of
hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6556A
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6556A with the
HIP660X family of Intersil MOSFET drivers, which require
12V bias.
high to enable the controller. This pin is typically
connected to the VID_PGOOD. The ISL6556ACB has
this signal internally connected high.
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either
of these codes and will execute soft start upon receiving
any other code. These codes can be used to enable or
disable the controller but it is not recommended. After
receiving one of these codes, the controller executes a
2-cycle delay before changing the over-voltage trip level
to the shut-down level and disabling PWM. Over-voltage
shutdown cannot be reset using one of these codes.
FAULT LOGIC
CIRCUIT
SOFT START
POR
ISL6556A INTERNAL CIRCUIT
AND
SENSITIVE ENABLE (EN) FUNCTION
ENABLE
COMPARATOR
+
-
1.24V
EXTERNAL CIRCUIT
VCC
EN
ENLL
(ISL6556ACR only)
10.7k
1.40k
+12V