ISL6556A Intersil Corporation, ISL6556A Datasheet - Page 15

• Manufacturer Part Number: ISL6556A
• Description: Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application
• Manufacturer: Intersil Corporation

Soft-Start
During soft start, the DAC voltage ramps linearly from zero
to the programmed VID level. The PWM signals remain in
the high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a pre-
existing charge on the output as the controller attempted to
regulate to zero volts at the beginning of the soft-start cycle.
The soft-start time, t
64 switching cycles followed by a linear ramp with a rate
determined by the switching period, 1/f
For example, a regulator with 250kHz switching frequency
having VID set to 1.35V has t
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft start and ramps to zero during the first 640
cycles of soft start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft start sees the DAC ramping
with 12.5mV steps.
Fault Monitoring and Protection
The ISL6556A actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 10
outlines the interaction between the fault monitors and the
power good signal.
t
SS
FIGURE 9. SOFT-START WAVEFORMS WITH AN UN-BIASED
=
64
-----------------------------------------
+
1280 VID
f
SW
OUTPUT. FSW = 500kHz
SS
, begins with a delay period equal to
2ms/DIV
VOUT, 500mV/DIV
500 s/DIV
15
SS
equal to 6.912ms.
SW
EN, 5V/DIV
.
(EQ. 10)
ISL6556A
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft start.
a successful soft start. PGOOD only transitions low when an
under-voltage condition is detected or the controller is
disabled by a reset from EN, ENLL, POR, or one of the
no-CPU VID codes. After an under voltage event, PGOOD
will return high unless the controller has been disabled.
PGOOD does not automatically transition low upon
detection of an over-voltage condition.
Under-Voltage Detection
The under-voltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the under-voltage
threshold, PGOOD gets pulled low.
Over-Voltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under Power on Reset in Electrical Specifications, the over-
voltage trip circuit is active using auxiliary circuitry. In this
state, an over-voltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the over-voltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
valid enable conditions being met as described in Enable
and Disable. The only exception to this is when the IC has
been disabled by an over-voltage trip. In that case the over-
voltage trip point is VID plus 200mV. During soft start, the
over-voltage trip level is the higher of 1.7V or VID plus
200mV. Upon successful soft start, the over-voltage trip level
is 200mV above VID. Two actions are taken by the
PGOOD pulls low during shutdown and releases high after
VDIFF
FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
REFERENCE
DAC
75%
VID + 0.2V
UV
AND CONTROL LOGIC
+
SOFT START, FAULT
-
OV
EACH CHANNEL
REPEAT FOR
OC
+
-
OC
+
-
100 A
I
1
PGOOD
OVP
100 A
I
AVG