BR24L01 Rohm, BR24L01 Datasheet

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BR24L01

Manufacturer Part Number
BR24L01
Description
1288 bit electrically erasable PROM
Manufacturer
Rohm
Datasheet

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Memory ICs
128 8 bit electrically erasable PROM
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W
BR24L01AFV-W / BR24L01AFVM-W
The BR24L01A-W series is 2-wire (I
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retention : 40 years
13) Filtered inputs in SCL SDA for noise suppression.
14) Initial data FFh in all address.
1) 128 registers 8 bits serial architecture.
2) Single power supply (1.8V to 5.5V).
3) Two wire serial interface.
4) Self-timed write cycle with automatic erase.
5) 8 byte page write mode.
6) Low power consumption.
7) DATA security
8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8
9) High reliability EEPROM with Double-Cell Structure
I
1
2, 3 Degradation is done at 4.5mW/ C for operation above 25 C.
4
5
Applications
Features
Absolute maximum ratings (Ta=25 C)
2
Supply voltage
Power dissipation
Storage temperature
Operating temperature
Terminal voltage
General purpose
C BUS is a registered trademark of Philips.
Write
Write protect feature (WP pin) .
Read
Standby (5V) : 0.1 A (Typ.)
Inhibit to WRITE at low V
Degradation is done at 8.0mW/ C for operation above 25 C.
Degradation is done at 3.0mW/ C for operation above 25 C.
Degradation is done at 3.1mW/ C for operation above 25 C.
Parameter
(5V) : 1.2mA (Typ.)
(5V) : 0.2mA (Typ.)
CC
Symbol
Topr
.
Tstg
V
Pd
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
CC
2
C BUS type) serial EEPROMs which are electrically programmable.
300 (SSOP-B8)
450 (SOP-J8)
310 (MSOP8)
0.3 to V
450 (SOP8)
800 (DIP8)
0.3 to 6.5
65 to 125
40 to 85
Limits
CC
0.3
BR24L01AFV-W / BR24L01AFVM-W
1
2
3
4
5
Unit
mW
V
C
C
V
1/25

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BR24L01 Summary of contents

Page 1

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 128 8 bit electrically erasable PROM BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W BR24L01AFV-W / BR24L01AFVM-W 2 The BR24L01A-W series is 2-wire ( BUS is a registered trademark of Philips. Applications General purpose Features 1) 128 registers 8 bits serial architecture. 2) Single power supply (1.8V to 5.5V). 3) Two wire serial interface. ...

Page 2

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Recommended operating conditions Parameter Symbol Supply voltage V CC Input voltage operating characteristics (Unless otherwise specified Ta VCC=1.8 to 5.5V) Parameter Symbol "HIGH" input volatge 1 V IH1 "LOW" input volatge 1 V IL1 "HIGH" input volatge 2 V IH2 " ...

Page 3

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Dimension 9.3 0 2.54 0.5 0.1 Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L01A-W) 4.9 0 1.27 0.42 0.1 Fig.1(c) PHYSICAL DIMENSION (Units : mm) SOP-J8 (BR24L01AFJ-W) 2.9 0 0.475 0.05 0.22 0.04 0.65 0.08 S Fig.1(e) PHYSICAL DIMENSION (Units : mm) MSOP8 (BR24L01AFVM-W) BR24L01AFV-W / BR24L01AFVM-W 7. Fig.1(b) PHYSICAL DIMENSION (Units : mm) ...

Page 4

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Block diagram A0 1 7bit A1 2 Address decoder A2 3 High voltage generator GND 4 Pin configuration Pin name Pin name Power supply CC GND Ground (0V) IN Slave address set A0, A1, A2 SCL IN Serial clock input Slave and word address, ...

Page 5

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs AC operating characteristics (Unless otherwise specified Ta Parameter Clock frequency Data clock "HIGH" period Data clock "LOW" period SDA and SCL rise time 1 SDA and SCL fall time 1 Start condition hold time Start condition setup time ...

Page 6

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Synchronous data timing SCL t STA HD : SDA (IN) t BUF SDA (OUT) SCL t : STA SU SDA SDA data is latched into the chip at the rising edge of SCL clock. Output data toggles at the falling edge of SCL clock. Write cycle timing SCL ...

Page 7

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs WP timing SCL DATA ( SDA ACK SCL DATA ( SDA ACK WP Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes first byte until the end of t ...

Page 8

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Device operation 1) Start condition (Recognition of start bit) All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met ...

Page 9

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 6) Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is -COM. When outputting the data in the read operation this device ...

Page 10

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Byte write SLAVE R ADDRESS T SDA LINE WP By using this command, the data is programmed into the indicated word address. When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array ...

Page 11

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Current read SDA 1 LINE In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). ...

Page 12

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Sequential read SLAVE A R ADDRESS D T SDA LINE Acknowledge is detected, and no STOP condition is generated by the master ( -COM), the device will continue to transmit the data. It can transmit all data (1kbit 128word Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode ...

Page 13

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs Application 1) WP effective timing WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to WP effective timing as follows. During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective period ...

Page 14

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 2) Software reset Please execute software reset in case that the device is an unexpected state after power up and / or the command input need to be reset. There are some kinds of software reset. Here we show three types of example as follows. During dummy clock, please release SDA bus ( tied to V During that time, the device may pull the SDA line LOW for Acknowledge or outputting or read data ...

Page 15

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 3) Acknowledge polling Since the device ignore all input commands during the internal write cycle, no ACK will be returned. When the master send the next command after the wire command, if the device returns the ACK, it means that the program is completed ...

Page 16

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 4) Command cancellation by start and stop condition During a command input canceled by the successive inputs of start condition and stop condition. (Fig.4) But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop condition is impossible, so that the reset can’ ...

Page 17

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 5) Notes for power supply V rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device CC may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of P.O.R. and LV In the case of power up, keep the following conditions to ensure functions of P.O.R and LV ( necessary to be “ ...

Page 18

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs LV circuit CC LV circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LV CC (Typ.=1.2V), write operation is inhibited circuit Pull up resister of SDA pin The pull up resister is needed because SDA is NMOS open drain. Decide the value of this resister (R ...

Page 19

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs The minimum value R PU The minimum value determined by following factors. PU Meet the condition that V OLMAX (=0.4V) must be lower than the input LOW level of the controller and the EEPROM including OLMAX recommended noise margin (0 ...

Page 20

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 8) Notes for noise About bypass capacitor Noise and surges on power line may cause the abnormal function recommended that the bypass capacitors (0.1 F) are attached on the V and GND line beside the device. CC The attachment of bypass capacitors on the board near by connector is also recommended. ...

Page 21

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs The maximum value The maximum value determined by following factors. S SDA rise time determined by R And the other timing must also keep the conditions of the AC timing. When the device outputs LOW on SDA line, the voltage of the bus A determined by R lower than the inputs LOW level of the controller, including recommended noise margin (0 ...

Page 22

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 10) The special character DATA The following characteristic data are typ value SPEC SUPPLY VOLTAGE : V (V) CC Fig.17 High input voltage V IH (A0,A1,A2,SCL,SDA,WP) 1 0.8 0.6 SPEC 0 0 ...

Page 23

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 0.6 SPEC 0.5 f 100kHz SCL 0.4 DATA AAh 0 0.2 0 SUPPLY VOLTAGE : V (V) CC Fig.26 Read operating current 100kHz) CC SCL 5 SPEC2 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE SPEC1 ...

Page 24

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 300 SPEC2 200 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE SPEC1 100 100 200 SUPPLY VOLTAGE : V (V) CC Fig.35 Input data setup time t (HIGH) SU:DAT 4 SPEC2 3 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE ...

Page 25

... BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W / Memory ICs 0.6 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0.2 0.1 SPEC1 SUPPLY VOLTAGE : V (V) CC Fig.44 Noise spike width t (SCL H) I 0.6 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0 0.2 0.1 SPEC1 SUPPLY VOLTAGE : V (V) CC Fig ...

Page 26

... Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any ...

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