BR24L01 Rohm, BR24L01 Datasheet - Page 10
BR24L01
Manufacturer Part Number
BR24L01
Description
1288 bit electrically erasable PROM
Manufacturer
Rohm
Datasheet
1.BR24L01.pdf
(26 pages)
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Memory ICs
Byte write
Page write
By using this command, the data is programmed into the indicated word address.
When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
This device is capable of eight byte page write operation.
When two or more byte data are inputted, the three low order address bits are internally incremented by one after the
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will
array.
receipt of each word. The four higher order bits of the address (WA6 to WA3) remain constant.
“roll over”, and the previous transmitted data will be overwritten.
LINE
WP
SDA
LINE
WP
SDA
R
S
T
A
T
1 0
S
A
R
T
T
ADDRESS
1
SLAVE
1 0
0
A2
ADDRESS
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
A1
1
SLAVE
A0
0
W
W
R
R
A2
T
E
I
/
C
A
K
A1
A0
WA
Fig.9 PAGE WRITE CYCLE TIMING
Fig.8 BYTE WRITE CYCLE TIMING
6
ADDRESS (n)
W
W
R
R
T
E
I
/
WORD
A
C
K
WA
BR24L01AFV-W / BR24L01AFVM-W
6
ADDRESS
WA
0
WORD
C
A
K
D7
DATA (n)
WA
0
C
A
K
D7
D0
C
A
K
DATA
DATA (n+7)
D0
A
C
K
D0
O
S
T
P
A
C
K
O
S
T
P
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