BR24L01 Rohm, BR24L01 Datasheet - Page 11

• Manufacturer Part Number: BR24L01
• Description: 1288 bit electrically erasable PROM
• Manufacturer: Rohm

Memory ICs
Current read
Random read
In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the
If an Acknowledge is detected, and no STOP condition is generated by the master ( -COM), the device will continue
If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
Random read operation allows the master to access any memory location indicated word address.
If an Acknowledge is detected, and no STOP condition is generated by the master ( -COM), the device will continue to
If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
internal address counter is increased by one from the last accessed address (n).
Thus Current Read outputs the data of the next word address (n+1).
If the last command is Byte or Page Write, the internal address counter stays at the last address (n).
Thus Current Read outputs the data of the word address (n).
to transmit the data. It can transmit all data (1kbit 128word)
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
transmit the data. It can transmit all data (1kbit 128word)
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
LINE
SDA
S
T
A
R
T
1
LINE
SDA
0
ADDRESS
1
SLAVE
0 A2A1A0
R
S
T
A
T
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
1
W
W
R
R
T
E
/
I
0
A
C
K
ADDRESS
1
SLAVE
Fig.10 CURRENT READ CYCLE TIMING
WA
Fig.11 RANDOM READ CYCLE TIMING
6
0 A2 A1 A0
ADDRESS(n)
WORD
BR24L01AFV-W / BR24L01AFVM-W
WA
W
R
E
A
D
R
0
/
A
C
K
C
A
K
S
A
R
T
T
D7
1
0
ADDRESS
1
SLAVE
0
DATA
A2A1A0
W
R
E
A
D
R
/
A
C
K
D7
D0
DATA(n)
A
C
K
O
S
P
T
D0
C
A
K
O
S
T
P
11/25