MT58L64V36F Micron Semiconductor, MT58L64V36F Datasheet - Page 17

• Manufacturer Part Number: MT58L64V36F
• Description: (MT58LxxxLxxF) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
READ/WRITE TIMING PARAMETERS
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_C.p65 – Rev. C, Pub. 11/02
BWa#-BWd#
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
KQ
OELZ
OEHZ
AS
ADSS
ADDRESS
(NOTE 4)
(NOTE 2)
BWE#,
ADSC#
ADSP#
ADV#
OE#
CLK
CE#
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
D
Q
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
8.0
1.8
1.8
1.8
1.8
0
-6.8
A1
125
6.8
3.8
High-Z
t ADSS
t CES
t AS
8.8
1.9
1.9
2.0
2.0
Q(A1)
Back-to-Back READs
0
A2
-7.5
t ADSH
t CEH
t KH
t AH
113
7.5
4.2
t KC
t KL
10.0
1.9
1.9
2.0
2.0
Q(A2)
0
-8.5
t OEHZ
100
8.5
5.0
A3
4.0
4.0
2.5
2.5
15
0
-10
READ/WRITE TIMING
10.0
5.0
66
Single WRITE
t WS
t DS
D(A3)
MHz
t DH
t WH
ns
ns
ns
ns
ns
ns
ns
ns
17
FLOW-THROUGH SYNCBURST SRAM
A4
t OELZ
SYMBOL
t
t
t
t
t
t
t
t
WS
DS
CES
AH
ADSH
WH
DH
CEH
t KQ
Q(A4)
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
(NOTE 1)
Q(A4+1)
BURST READ
-6.8
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
Q(A4+2)
-7.5
Q(A4+3)
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
DONÕT CARE
-8.5
D(A5)
©2002, Micron Technology, Inc.
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
A5
Back-to-Back
-10
WRITEs
UNDEFINED
D(A6)
A6
ns
ns
ns
ns
ns
ns
ns
ns