MT28F160C34 Micron Technology, MT28F160C34 Datasheet - Page 13

• Manufacturer Part Number: MT28F160C34
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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SOFT BLOCK DATA PROTECTION
(see Table 3). The protection bit for each block can be set
and cleared individually, or all at once. After the soft
protection bit of a block is set, the block is protected when
V
V
unlocked when WP# is HIGH, even if its soft protection
bit is set (see Table 5).
protection bits will be set to the protected state. If WP#
goes LOW after first power-up, reset, or power-down, all
blocks are protected. The CSM command 0Fh is needed
to clear the soft protected blocks. When WP# goes LOW,
the cleared blocks are unprotected.
individual block lock status after the second WRITE cycle
of the soft protection CSM command. Additionally, to
monitor the block lock status of any block, the read status
register command 70h can be used. On the command’s
second cycle, any address within a block is issued and
SR1 indicates the block lock status for that block. When
monitoring the block lock status bit SR1, the correct
status can only be obtained with WP# LOW.
1 Meg x 16 3V Enhanced+ Boot Block Flash Memory
MT28F160C34_3.p65 – Rev. 3, Pub. 8/01
4
PP
PPLK
U
Soft protection is available with CSM command 0Fh
When the device is powered down or reset, the soft
The block lock status bit SR1 is used to monitor the
.com
V
the block is protected (locked) as well. A block is
PPLK
, RP# is HIGH, and WP# is LOW. When V
3V ENHANCED+ BOOT BLOCK FLASH MEMORY
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PP
13
POWER-UP
V
RP# be held LOW during power-up for additional protec-
tion while V
level. After a power-up or RESET, the status register is
reset, and the device will enter the array read mode.
POWER-UP PROTECTION
tions is minimized since two consecutive cycles are re-
quired to execute either operation. When V
device does not accept any WRITE cycles, and noise
pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.
POWER SUPPLY DECOUPLING
0.1µF ceramic capacitor connected between V
V
should be as close as possible to the device balls.
CC
PP
During a power-up, it is not necessary to sequence
The likelihood of unwanted WRITE or ERASE opera-
For decoupling purposes, each device should have a
and V
Q, V
CC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
, and V
CC
, and between V
is ramping above V
PP
. However, it is recommended that
CC
Q and V
LKO
1 MEG x 16
to a stable operative
SS
©2001, Micron Technology, Inc.
. The capacitor
ADVANCE
CC
< V
CC
and V
LKO
, the
SS
,