PIC18LF13K22 Microchip Technology, PIC18LF13K22 Datasheet - Page 17

• Manufacturer Part Number: PIC18LF13K22
• Description: (PIC18F1xK22) Flash Microcontrollers
• Manufacturer: Microchip Technology

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4.2.1
The previous programming example assumed that the
device has been Bulk Erased prior to programming
(see Section 4.1.1 “High-Voltage ICSP Bulk Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
TABLE 4-6:
© 2008 Microchip Technology Inc.
Step 1: Direct access to code memory.
Step 2: Read code memory into buffer (Section 5.1 “Read Code Memory, ID Locations and Configuration Bits”).
Step 3: Set the Table Pointer for the block to be erased.
Step 4: Enable memory writes and setup an erase.
Step 5: Initiate erase.
Step 6: Poll WR bit. Repeat until bit is clear.
Step 7: Load write buffer. The correct bytes will be selected based on the Table Pointer.
To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 4-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of the
erase buffer.
Step 8: Disable writes.
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1111
0000
0000
4-bit
•
•
•
MODIFYING CODE MEMORY
MODIFYING CODE MEMORY
0E <Addr[21:16]>
0E <Addr[21:16]>
0E <Addr[8:15]>
0E <Addr[8:15]>
0E <Addr[7:0]>
0E <Addr[7:0]>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
Data Payload
9C A6
8E A6
6E F8
6E F7
6E F6
84 A6
88 A6
88 A6
82 A6
50 A6
6E F5
6E F8
6E F7
6E F6
94 A6
00 00
00 00
00 00
00 00
•
•
•
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
BSF
NOP
NOP
MOVF
MOVWF
NOP
Shift out data
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
BCF
Advance Information
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, WREN
EECON1, FREE
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
EECON1, FREE
EECON1, WR
Erase starts on the 4th clock of this instruction
EECON1, W, 0
TABLAT
PIC18F1XK22/LF1XK22
(1)
The appropriate number of bytes required for the erase
buffer must be read out of code memory (as described
in Section 5.2 “Verify Code Memory and ID Loca-
tions”) and buffered. Modifications can be made on
this buffer. Then, the block of code memory that was
read out must be erased and rewritten with the
modified data.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
Core Instruction
DS41357A-page 17