PIC18LF13K22 Microchip Technology, PIC18LF13K22 Datasheet - Page 12

no-image

PIC18LF13K22

Manufacturer Part Number
PIC18LF13K22
Description
(PIC18F1xK22) Flash Microcontrollers
Manufacturer
Microchip Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF13K22-I/ML
Manufacturer:
CAVIUM
Quantity:
155
Part Number:
PIC18LF13K22-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
www.DataSheet4U.com
PIC18F1XK22/LF1XK22
FIGURE 4-2:
4.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 4.1.3 “ICSP Row Erase” and Section 4.2.1
“Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 4.3
“Data EEPROM Programming” and write ‘1’s to the
array.
DS41357A-page 12
PGC
PGD
4-bit Command
1
0
LOW-VOLTAGE ICSP BULK ERASE
2
0
3
1
4
1
P5
BULK ERASE TIMING DIAGRAM
1
1
Data Payload
2
1
16-bit
15 16
0
0
P5A
4-bit Command
1
0
Advance Information
2
0
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-bit
4.1.3
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 3.0 “Memory
Maps”).
The Row Erase duration is self-timed. After the WR bit
in EECON1 is set, two NOPs are issued. Erase starts
upon the 4th PGC of the second NOP. It ends when the
WR bit is cleared by hardware.
The code sequence to Row Erase a PIC18F1XK22/
LF1XK22 device is shown in Table 4-3. The flowchart
shown in Figure 4-3 depicts the logic necessary to com-
pletely erase the PIC18F1XK22/LF1XK22 devices. The
timing diagram for Row Erase is identical to the data
EEPROM write timing shown in Figure 4-7.
15 16
Note:
0
0
P5A
4-bit Command
1
ICSP ROW ERASE
The TBLPTR register can point at any byte
within the row intended for erase.
0
2
0
3
0
4
0
© 2008 Microchip Technology Inc.
Erase Time
P11
P10
Data Payload
16-bit
1
n
2
n

Related parts for PIC18LF13K22