KSC-1000 Kodak, KSC-1000 Datasheet
KSC-1000
Related parts for KSC-1000
KSC-1000 Summary of contents
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... IMAGE SENSOR SOLUTIONS KODAK KSC-1000 Timing Generator July 12, 2003 Revision 1 ...
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IMAGE SENSOR SOLUTIONS TABLE OF CONTENTS TABLE OF FIGURES .................................................................................................................................................... 3 TABLE OF TABLES ...................................................................................................................................................... 3 SUMMARY SPECIFICATION........................................................................................................................................ 4 DEVICE DESCRIPTION................................................................................................................................................ 5 A ........................................................................................................................................................... 5 RCHITECTURE Overall ................................................................................................................................................................. 5 Sequence of Operations ...................................................................................................................................... 6 Horizontal Line Synchronization .......................................................................................................................... 8 Pin ...
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... IGURE TABLES T 1 KSC-1000 P D ABLE KSC-1000 A ABLE BSOLUTE T 3 KSC-1000 R ABLE ECOMMENDED ABLE OWER UPPLY T 5 KSC-1000 DC C ABLE T 6 KSC-1000 AC C ABLE ABLE SCILLATOR UFFER T 8 DLL S ABLE PECIFICATIONS ABLE ERIAL NTERFACE T ...
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... IMAGE SENSOR SOLUTIONS SUMMARY SPECIFICATION KODAK KSC-1000 Timing Generator Description The Kodak KSC-1000 simplifies camera design by providing all of the timing signals necessary to operate the entire family of Kodak area array image sensors (Full Frame and Interline CCDs) and associated analog front-end (AFE) circuits. Full program- ability through a simple 3-wire serial interface allows maximum flexibility in sensor operation ...
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... Crit Path Outputs ow_outputs dll_clk(31:0) serial_if vd_sync ext_sync hd_sync clock_buffers ksc1000_dll dll_control dll_clk_in, dll_reset, clk0_free_run Figure 1 KSC 1000 Block Diagram fast_dump fast_dump v1_1 v1_1 v1_2 v1_2 v2_1 v2_1 v2_2 v2_2 vdischg vdischg integrate_start integrate_start ...
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... The output of the DLL an external controller. The KSC-1000 supports imager array sizes up to 8192 pixels by 8192 pixels. Gray coding is used on the internal horizontal pixel counter to minimize the risk of digital noise coupling into the analog signal processing ...
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... E No INTG_STRT Sequence Start Horizontal Pixel Counter Yes Run Horizontal Pixel Counter Figure 2 KSC-1000 Sequence Flow Diagram Terminal Count Next Frame Table Yes reached Instruction ...
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... driven low. controller to synchronize horizontal line readout. Holding the HD signal low gives the KSC-1000 full control over horizontal line readout. HD functionality is illustrated in Figure 3. Pixels Per Line Figure 3 HD Functionality ...
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... Figure 4 KSC-1000 Pin Diagram Vertical Phase Discharge Switch Control Output 3.3V I/O Power Supply Vertical Clock Phase 2 Output 2 1.8V DLL Power Supply 1.8V Core Logic Power Supply Vertical Clock Phase 2 Output 1 Vertical Clock Phase 1 Output 2 ...
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IMAGE SENSOR SOLUTIONS 9 VDD_IO 10 V1_1 11 VDD_C 12 VDD_IO 13 H2_2 14 HLG_2 15 H1_2 16 VDD_IO H2_1 19 VDD_C 20 HLG_1 21 VDD_IO 22 H1_1 23 SHP_2 24 VDD_C 25 SHP_1 26 SHD_2 27 ...
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... Ground 1.8V Core Logic Power Supply Serial Clock Input 3.3V I/O Power Supply Serial Data I/O Serial Load Input Video Amplifier Enable Control Output Integration initiation pulse Table 1 KSC-1000 Pin Descriptions ...
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... VDD_C VDD_DLL STG Table 2 KSC-1000 Absolute Maximum Ratings Symbol Min Typ VDD_IO 3.0 3.3 VDD_DLL 1.7 1.8 1.7 1.8 T -20 OPR Table 3 KSC-1000 Recommended Operating Conditions Min Max VSS – 0.3 4.6 VSS – 0.3 2.5 VSS – 0.3 2.5 VSS – 0.3 VDD_IO + 0.3 -55 +150 Max Unit 3.6 V 1.9 V 1.9 V +70 ° ...
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... A single, common ground plane is recommended to reduce ground loops and local Eddy currents. The Micro Lead Frame (MLF) package of the KSC-1000 has a die attach ‘paddle’ on the PCB side of the package. This paddle is connected internally to the VSS nodes for VDD_C, VDD_IO, and VDD_DLL. It must be externally connected to the ground plane of the PCB during manu- facturing ...
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IMAGE SENSOR SOLUTIONS Power Dissipation Power dissipation is a function of the operating frequency, the number of outputs that are enabled, and the drive level of the pixel rate outputs. The table below lists current require- Frequency VDD_DLL (MHz) (mA ...
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... I = 50uA OL OUT Low Level Output Current I = 8mA OUT I Maximum Output Current Omax I Maximum Output Current Omax Table 5 KSC-1000 DC Characteristics Min Typ Max Unit 2 ...
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... Low Speed Clock Fall Time FV t Rise Time Delta Propagation PDRV Delay t Fall Time Delta Propagation PDFV Delay Table 6 KSC-1000 AC Characteristics T RH 90% 10% Figure 5 Pixel Rate Signal Rise and Fall Time Min Typ Max Units 445 ...
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IMAGE SENSOR SOLUTIONS V OH AMP_EN, CLPDM, CLPOB, FAST_DUMP, FRAME_VAL, LINE_VAL, PBLK, SHUTTER, V1_1, V1_2, V2_1, V2_2, VDISCHG PIXCLK ADCLK, DATACLK, H1_1, H1_2, H2_1, H2_2, HLG_1, HLG_2, RG, SHD_1, SHD_2, SHP_1, SHP_2, ...
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IMAGE SENSOR SOLUTIONS V OH PIXCLK AMP_EN, CLPDM, CLPOB, FAST_DUMP,FRAME_VAL, LINE VAL, PBLK, SHUTTER, V1_1, V1_2, V2_1, V2_2, VDISCGH Figure 8 Line and Frame Rate Signal Rise and Fall Time Delta Propagation Delay K ...
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IMAGE SENSOR SOLUTIONS Oscillator Buffer Characteristics Pin Name Symbol Xtal_I f Xtal_O On Chip R1 Resistor TC1 TC2 XTAL_O R1 = 1Meg (on chip - No external R1 component required) XTAL_I ...
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IMAGE SENSOR SOLUTIONS DLL Specifications Pin Name Parameter Lock Range CLK_IN Lock Time (input) Duty Cycle Input Clk Freq Output Clk Freq. Output Clk Phase Increment CLK(0:63) Output Clk Tap (output) Tolerance Output Clk Duty Cycle ...
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... IMAGE SENSOR SOLUTIONS SERIAL INTERFACE SPECIFCATIONS Timing Specifications The KSC-1000 utilizes a 3 wire serial interface. Both read and write operations are supported. Individual Registers can be written/read by writing the appropriate asserting SCLK only for the number of bits in that register. Multiple written/read by writing the appropriate starting address and asserting SCLK for the total number of bits in the desired registers ...
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IMAGE SENSOR SOLUTIONS LSB 1 A0 RNW SDATA t ds SCLOCK t ls SLOAD Note 1: RNW Read-Not-Write. Set low for write operation and high for read operation. Parameter SCLK frequency f sck SLOAD to SCLK setup time t ls ...
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... DLL Locked Table 10 Serial Interface Register Map Register is set. The low power mode is the only The mode where the operation of KSC-1000 is pre- determined and therefore does not require a unique frame table. KSC-1000 supports frame tables. The numbering of the frame tables is arbitrary ...
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IMAGE SENSOR SOLUTIONS General Setup Register The General Setup Register controls the following parameters: Horizontal Line Length Line sync start and stop pixel locations AFE clamping signal start and stop pixel locations AFE blanking signal start and stop pixel locations ...
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IMAGE SENSOR SOLUTIONS Register 1 Data Length Register Field 13 bits Pixels Per Line 13 bits Line Valid Pixel Start 2 bits Line Valid Pixel Quadrature Start 13 bits Line Valid Pixel End 13 bits CLPOB1_Pix_Start (Dark Line Frame Rate ...
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IMAGE SENSOR SOLUTIONS 1 bit H1_2 24mA output enable (0 = 12mA 24mA) 1 bit H2_2 24mA output enable (0 = 12mA 24mA) 1 bit HLG_2 24mA output enable (0 = 12mA 24mA) 1 ...
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... Power Management Operation state The Low Power Enable bit is used to place the KSC-1000 in its low power mode. In this mode the DLL and other clocks except PIXCLK are shut down. Serial programming is enabled in the low power mode. The RAM tables and all registers retain their settings ...
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... IMAGE SENSOR SOLUTIONS INTG_STRT Setup Register Electronic shuttering is used with the Kodak family of interline sensors. illustrates the electronic shutter timing with respect to the image sensor horizontal and vertical clocks the electronic shutter setup essu time, is the time from the end of the horizontal clocks to the start of the electronic shutter pulse ...
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IMAGE SENSOR SOLUTIONS INTG_STRT Line Register The value in this INTG_STRT clock sequence described in the Integrate Start Setup Register at the start of the programmed line number. counter starts at count 0 and counts up. Note Register 4 Data ...
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... ASIC) 1 bit V2_1_IDLE_VAL (used in conjunction with V2_2 to define non-clocking state of KSC- 2000 clock driver ASIC) 1 bit V2_2_IDLE_VAL (used in conjunction with V2_1 to define non-clocking state of KSC- 2000 clock driver ASIC) 1 bit V_DISCHG_IDLE_VAL (level held during de-asserted state) 1 bit FAST_DUMP_IDLE_VAL (level held during de-asserted state ...
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IMAGE SENSOR SOLUTIONS Offset Register This register controls the offset of the leading edge of the signals listed below relative to the DLL clk(0) signal for given output. Register 6 Data Length 6 bits H1_1_OFFSET 6 bits H1_2_OFFSET 6 bits ...
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IMAGE SENSOR SOLUTIONS Width Register This register controls the width of the signals listed below. The width is defined in units of th 1/64 the pixel period. Each entry is 5 bits in length, providing a maximum width of ½ ...
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IMAGE SENSOR SOLUTIONS Register 8 Data Length 7 bits 34 bits Bit Location Name 0:3 Entry Number One of 16 possible entries (15:0). Each entry points to a line table to define the 4:6 Table Number One of 8 possible ...
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IMAGE SENSOR SOLUTIONS Enable 9 AFE Clock Enable 0 = De-assert ADCLK, DATACLK, SHP_1, SHP_2, SHD_1, SHD_2 10 CLPDM2 Enable 11 CLPDM1 Enable 12 CLPOB2 Enable 13 CLPOB1 Enable 14 PBLK Enable 15 Pblk_Idle_Val 16 Flag 17:29 Count 30:32 Address ...
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IMAGE SENSOR SOLUTIONS Count Flag VD Event > > Horizontal Binning Factor ...
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IMAGE SENSOR SOLUTIONS Line Table Access Register The Line Table Access Register is used to program the Line Tables. Programming of the Line Tables is permitted only in low power mode or when the Memory Table Mode bit of the ...
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IMAGE SENSOR SOLUTIONS Status Register The Status Register is a read only register which provides DLL, Frame Table, Line Table, and VD status. Register 10 Data Length 1 bit DLL Locked DLL not locked DLL locked ...
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... IMAGE SENSOR SOLUTIONS MECHANICAL DRAWINGS Package Figure 13 KSC-1000 Package Drawing Page ...
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... IMAGE SENSOR SOLUTIONS Figure 14 KSC-1000 Package Drawing Page ...
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IMAGE SENSOR SOLUTIONS PC Board Geometry and Attachment The package is a 8mm x 8mm Micro leadframe (MLF) package. The package itself is Lead (Pb) free, with a Cu-alloy lead frame and pure tin plating. The package has been qualified ...
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... IO Pad Center to Center G Via Hole Spacing Figure 15 KSC-1000 PC Board Geometry Description Distance (mm) Table 29 KSC-1000 PC Board Geometry Dimensions Distance (mils) 3.5 137.78 0.69 27.16 1.74 68.49 0.28 11.10 ...
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... Solder Pattern Length (Solder Stencil Defined) B Solder Pattern Width(Solder Stencil Defined) C Solder Mask Via “tent” diameter Table 30 KSC-1000 Ground Paddle Solder Stencil and Solder Mask Dimensions ...
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... IMAGE SENSOR SOLUTIONS Package Moisture Sensitivity Level The KSC-1000 MLF package has Moisture Sensitivity Level (MSL) rating of 3. The devices are shipped in a vacuum-sealed bag. The shelf life in the bag is 12 months when stored at a temperature of less than 40˚C and a relative humidity level of less than 90% ...
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IMAGE SENSOR SOLUTIONS QUALITY ASSURANCE AND RELIABILITY Quality Strategy: All CCD timing generators will conform to the specifications stated in this document. This will be accomplished through a combination of statistical process control and inspection at key points of the ...
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... Type Description KSC-1000 CCD Timing Generator ...
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IMAGE SENSOR SOLUTIONS REVISION CHANGES Revision Number ...