MD2241-D128-V3 M-Systems Inc., MD2241-D128-V3 Datasheet - Page 39

• Manufacturer Part Number: MD2241-D128-V3
• Description: Diskonchip Dimm Plus
• Manufacturer: M-Systems Inc.

10.4.3 Power-Up Timing
DiskOnChip DIMM Plus is reset by assertion of the RSTIN# input. When this signal is asserted, DiskOnChip
initiates a download procedure from the flash memory into the internal XIP of the Programmable Boot Block.
During this procedure, DiskOnChip DIMM Plus does not respond to read or write accesses.
Host systems that boot from DiskOnChip DIMM Plus must employ either option c below or another method to
guarantee the required timing of the first access. All other host systems can employ any of the following methods to
guarantee first-access timing requirements:
39
1. Specified from the final positive crossing of Vcc above 2.7V.
2. If the assertion of RSTIN# occurs during a flash erase cycle, this time could be extended by up to 500µS.
3. Normal read/write cycle timing applies. This parameter applies only when the cycle is extended until the negation of the BUSY# signal.
a.
b. Poll the state of the BUSY# output.
c.
Use a software loop to wait at least Tp (BUSY1) before accessing the device after the reset signal is
negated.
Use the BUSY# output to hold the host CPU in wait state before completing the first access.
T
Tp (VCC-BUSY0)
REC
T
D (Read cycle)
T
HO
SU
T
T
T
P
P
W
Symbol)
(VCC-RSTIN)
(BUSY-CE)
(D-BUSY1)
(BUSY1)
(BUSY0)
(RSTIN)
RSTIN#
BUSY#
Operating Voltage
CE#
Vcc
Vcc Minimum
2
3
3
1
1
Table 12: Power Up Timing Definitions
Preliminary Data Sheet, Rev. 1.2
RSTIN# asserted pulse width
Figure 16: Reset Timing
VCC stable to RSTIN#
VCC stable to BUSY#
RSTIN#
RSTIN#
T
Data valid to BUSY#
T
T
T
P
BUSY#
P
W
REC
(BUSY0)
(VCC_BUSY0)
(RSTIN)
Description
(VCC-RSTIN)
to BUSY#
to BUSY#
to CE#
T
SU
(D-BUSY1)
T
P
(BUSY1)
Min
500
30
0
0
T
HO
(BUSY-CE)
Max
500
1.3
50
DiskOnChip DIMM Plus
94-SR-002-08-8L
Units
ms
µs
µs
ns
ns
ns
ns