MD2241-D128-V3 M-Systems Inc., MD2241-D128-V3 Datasheet - Page 32

• Manufacturer Part Number: MD2241-D128-V3
• Description: Diskonchip Dimm Plus
• Manufacturer: M-Systems Inc.

9.2.2 Connecting Signals
DiskOnChip DIMM Plus uses standard SRAM-like control signals, which should be connected as follows:
DiskOnChip DIMM Plus derives its internal clock signal from the CE#, OE# and WE# inputs. Since access to
DiskOnChip DIMM Plus’ registers is volatile, much like a FIFO or UART, ensure that these signals have clean
rising and falling edges, and are free from ringing that can be interpreted as multiple edges. PC board traces for
these three signals must either be kept short or properly terminated to guarantee proper operation.
9.3
The following section describes hardware design issues.
9.3.1 Wait State
Wait states can be implemented only when DiskOnChip DIMM Plus is designed in a bus that supports a Wait state
insertion, and supplies a WAIT signal.
9.3.2 Big and Little Endian Structures
PowerPC, ARM, and other RISC processors can use either Big or Little Endian structures. The DiskOnChip is a
Little Endian device. Therefore bytes D[7:0] are its Least Significant Byte (LSB) and bytes D[15:8] are its Most
Significant Byte (MSB). Within the bytes, bit D0 and bit D8 are the least significant bits of their respective byte.
When connecting the DiskOnChip to a Big Endian device, make sure to that the bytes of the CPU and the
DiskOnChip match.
Note: Processors, such as the PowerPC, also change the bit ordering within the bytes. Failing to follow these rules
9.3.3 Busy Signal
The Busy signal (BUSY#) indicates that DiskOnChip DIMM Plus has not yet completed internal initialization. After
reset, BUSY# is asserted while the IPL is downloaded into the internal SRAM and the Data Protection Structures
(DPS) are downloaded to the Protection State Machines. Once the download process is completed, BUSY# is
negated. It can be used to delay the first access to DiskOnChip DIMM Plus until it is ready to accept valid cycles.
Note: The TrueFFS driver does NOT use this signal to indicate that the flash is in busy state (e.g. program, read, or
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Platform-Specific Issues
will result in improper connection of the DiskOnChip and will prevent the TrueFFS driver from identifying
the DiskOnChip.
erase).
Address (A[12:0]) – Connect these signals to the host address bus.
Data (D[15:0]) – Connect these signals to the host data bus.
Write (WE#) and Output Enable (OE#) – Connect these signals to the host WR# and RD# signals,
respectively.
Chip Enable (CE#) – Connect this signal to the memory address decoder.
Power-On Reset In (RSTIN#) – Connect this signal to the host Power-On Reset signal.
Busy (BUSY#) – Connect this signal to an input port. It indicates when the device is ready for first access
after reset.
Byte High Enable (BHE#) – This signal definition is compatible with 16 bit platforms that use the
BHE#/BLE# protocol. See section 8.3.4. This signal is only relevant during the boot phase.
Hardware Lock (LOCK#) – This signal prevents the use of the Write Protect Key to disable the protection.
8/16 bit Configuration (IF_CFG) – This signal is required for configuring the device for 8 or 16-bit access
mode. When negated, the device is configured for 8-bit access mode. When asserted, 16-bit access mode is
operative.
Preliminary Data Sheet, Rev. 1.2
DiskOnChip DIMM Plus
94-SR-002-08-8L