MD2241-D128-V3 M-Systems Inc., MD2241-D128-V3 Datasheet - Page 20

• Manufacturer Part Number: MD2241-D128-V3
• Description: Diskonchip Dimm Plus
• Manufacturer: M-Systems Inc.

section 10.4.1 be met. It is also essential that read and write cycles are not interrupted by glitches or ringing on the
CE#, WE#, OE# address inputs.
Note:
In normal mode, DiskOnChip DIMM Plus responds to every valid hardware cycle. When there is no activity, power
consumption automatically drops to a typical standby current of 400µA.
5.2
In Reset mode, DiskOnChip DIMM Plus ignores all write cycles, except for those to the DiskOnChip Control
register and Control Confirmation register. All register read cycles return a value of 00H.
Before attempting to perform a register read operation, the device is set to Normal mode by TrueFFS software.
5.3
In Deep Power-Down mode, DiskOnChip DIMM Plus internal high current voltage regulators are disabled to reduce
quiescent power consumption. The following signals are also disabled in this mode: input buffers A[12:0], BHE#,
WE#, D[15:0] and OE# (when CE# is negated).
To enter Deep Power-Down mode, a proper sequence must be written to the DiskOnChip. In Deep Power-Down
mode, write cycles have no effect and read cycles return indeterminate data (DiskOnChip DIMM Plus does not drive
the data bus). Entering Deep Power-Down mode and then returning to the previous mode does not affect the value
of any register.
To exit Deep Power-Down mode, perform the following sequence:
Applications that require both Deep Power-Down mode and boot detection require BIOS support to ensure that
DiskOnChip DIMM Plus exits from Power-Down mode prior to the expansion ROM scan. Similarly, applications
that use DiskOnChip DIMM Plus as a boot ROM must ensure that the device is not in Deep Power-Down mode
before reading the boot vector/instructions, either by pulsing RSTIN# to the asserted state and waiting for the
BUSY# output to be negated, or by entering Reset mode via software.
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Deep Power-Down Mode
Reset Mode
All inputs to DiskOnChip DIMM Plus are Schmidt trigger types to improve noise immunity.
Read any address (1FFFH is suggested) three times. The data returned is undefined. The regulators are
enabled at the beginning of the first cycle. The input buffers (A[12:0], BHE#, WE#, D[15:0] and OE#) are
enabled at the end of the third cycle.
Read the selected address one more time (data returned is still undefined).
Preliminary Data Sheet, Rev. 1.2
DiskOnChip DIMM Plus
94-SR-002-08-8L