ADC1413D NXP Semiconductors, ADC1413D Datasheet - Page 37

• Manufacturer Part Number: ADC1413D
• Description: Dual 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 50.
Table 51.
ADC1413D_SER_4
Preliminary data sheet
Bit
5 to 4
3
2
1
0
Bit
7 to 6
5 to 4
3 to 1
0
Symbol
LANE_MODE[1:0]
-
LANE_POL
LANE_CLK_POS_EDGE R/W
Lane_PD
Symbol
-
ADC_MODE[1:0]
-
ADC_PD
LaneB_0_ctrl (address 0871h)
ADCA_0_ctrl (address 0890h)
Access
R/W
R
R/W
R/W
Access
R
R/W
R
R/W
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…continued
Value
00 (reset)
01
10
11
0
0
1
0
1
0
1
Value
00
00 (reset)
01
10
11
000
0
1
Rev. 04 — 23 April 2010
Description
defines output type of lane output unit:
not used
defines lane polarity:
defines lane clock polarity:
lane power-down control:
Description
not used
defines input type of JESD204A unit:
not used
ADC power-down control:
normal mode: Lane output is the 8b/10b output unit
constant mode: Lane output is set to a constant (0x0)
toggle mode: Lane output is toggling between 0x0 and 0x1
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_ctrl register)
lane polarity is normal
lane polarity is inverted
lane clock provided to the serializer is active on positive edge
lane clock provided to the serializer is active on negative edge
lane is operational
lane is in Power-down mode
ADC output is connected to the JESD204A input
not used
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_ctrl register)
ADC is operational
ADC is in Power-down mode
ADC1413D series; serial JESD204A interface
ADC1413D series
© NXP B.V. 2010. All rights reserved.
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