ADC1413D NXP Semiconductors, ADC1413D Datasheet - Page 14

• Manufacturer Part Number: ADC1413D
• Description: Dual 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
13. Application information
ADC1413D_SER_4
Preliminary data sheet
13.1.1 Input stage description
13.1 Analog inputs
The analog input of the ADC1413D supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Figure 6
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Fig 6.
shows the equivalent circuit of the sample and hold input stage, including
Input sampling circuit
I(cm)
INAM
INBM
INAP
INBP
) on pins INxP and INxM set to 0.5V
All information provided in this document is subject to legal disclaimers.
1, 14
2, 13
Rev. 04 — 23 April 2010
Package
ESD
ADC1413D series; serial JESD204A interface
Section 13.2
Parasitics
DDA
ADC1413D series
.
R on = 15 Ω
R on = 15 Ω
Internal
Internal
Switch
Switch
and
clock
clock
Table 21
4 pF
4 pF
C s
C s
005aaa069
for further details).
© NXP B.V. 2010. All rights reserved.
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