ADC1413D NXP Semiconductors, ADC1413D Datasheet
ADC1413D
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ADC1413D Summary of contents
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... SPI programmable full-scale to allow flexible input voltage range from (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1413D ideal for use in communications, imaging, and medical applications. 2. Features and benefits SNR, 72 dBFS ...
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... INPUT STAGE INBM ADC1413D Fig 1. Block diagram ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Package Name Description HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 × 8 × 0.85 mm HVQFN56 plastic thermal enhanced very thin quad flat package; ...
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... Fig 2. Pinning diagram 6.2 Pin description Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB INBM ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface INAP 1 INAM 2 VCMA 3 4 REFAT 5 REFAB AGND 6 CLKP 7 ADC1413D CLKM 8 AGND 9 10 ...
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... DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 DNC VDDA AGND AGND VDDA ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Pin description …continued [1] Pin Type Description 14 I channel B analog input 15 P analog power supply analog power supply 3 V ...
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... Thermal characteristics Table 4. Symbol R th(j-a) R th(j-c) [1] Value for six layers board in still air with a minimum of 25 thermal vias. ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Pin description …continued [1] Pin Type Description 54 I reference programming pin 55 I/O voltage reference input/output ...
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... SPI: pins CS, SDIO/DCS, and SCLK/DCS V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH C input capacitance I ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Conditions Min 2.85 1. 125 Msps; - clk f =70 MHz 125 Msps; - clk MHz ...
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... LOW-level output OL voltage V HIGH-level output OH voltage Output levels 1.8 V; SWING_SEL[2:0] = 100 DDD V LOW-level output OL voltage V HIGH-level output OH voltage ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Conditions Min −5 track mode track mode - track mode - track mode 0.9 - peak-to-peak output 0.5 input 0.5 DC coupled ...
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... Typical values measured DDA = −40 °C to +85 ° range T amb DDA 100 Ω differential applied to serial outputs; unless otherwise specified. ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Conditions Min differential; input - differential; input - −5 −0.95 no missing codes ...
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... ADC1413D125 Unit Typ Max Min Typ Max dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... Typ Max Min Typ Max - 100 - - 100 - = 25 °C. Minimum and maximum values are across the full temperature range T amb ADC1413D105 ADC1413D125 Unit Min Typ Max Min Typ Max - dBc - dBc - dBc - dBc - 100 ...
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... Minimum and maximum values are across the full temperature range T amb ADC1413D125 Unit Typ Max Min Typ Max - 105 100 - 125 Msps - 226 160 - 170 0 0 < ...
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... DC coupling with two different receiver common-mode voltages Fig 3. Eye diagram receiver common-mode Fig 4. Eye diagram receiver common-mode ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface All information provided in this document is subject to legal disclaimers. Rev. 04 — 23 April 2010 ADC1413D series www.DataSheet4U.com Figure 3 and Figure 4 ...
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... Typical values measured at V across the full temperature range T INBP) − V unless otherwise specified. Fig 5. SPI timings ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Characteristics Parameter Conditions SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time ...
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... NXP Semiconductors 13. Application information 13.1 Analog inputs 13.1.1 Input stage description The analog input of the ADC1413D supports differential or single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 8. Single transformer configuration ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Figure 7) is needed to counteract the effects coupling versus input frequency, typical values Resistance 25 Ω ...
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... System reference and power management 13.2.1 Internal/external reference The ADC1413D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an SENSE (see and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see ...
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... Table 10. Mode Internal (Figure Internal (Figure External (Figure Internal, SPI mode (Figure 14) ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface REFERENCE AMP EXT_ref EXT_ref BUFFER SELECTION LOGIC Reference modes SPI bit, “Internal SENSE pin reference” 11) 0 ...
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... ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface 005aaa116 Fig 12. Internal reference (p-p) full scale 005aaa119 Fig 14. Internal reference via SPI (p- (p-p) to Figure 14 indicate how to connect the SENSE and VREF pins. 21). The corresponding full scale input voltage range varies between 2 V (p-p) ...
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... INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 13.3 Clock input 13.3.1 Drive modes The ADC1413D can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor). a. Rising edge LVCMOS Fig 16 ...
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... Fig 18. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI (see single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface CLKP Sine clock input CLKM 005aaa173 ...
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... DCS_enable SPI 0 1 13.3.4 Clock input divider The ADC1413D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 13.4 Digital outputs 13 ...
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... CS bits for control N' = N+CS CF: position of controls bits S samples per frame cycle HD: frame boundary break Padding with Tails bits (TT) Mx(N'xS) bits Fig 21. General overview of the JESD204A serializer ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB 10 nF CMLNA/CMLNB 10 nF − ...
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... INP-INM (V) < −1 −1 −0.9998779 −0.9997559 −0.9996338 −0.9995117 .... −0.0002441 −0.0001221 0 +0.0001221 +0.0002441 ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface SCRAMB_IN_MODE[1: PRBS 01 FSM (f assy, char repl, ILA, test mode) PRBS ...
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... Serial Peripheral Interface (SPI) 13.6.1 Register description The ADC1413D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). ...
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... ADC channel will receive the next SPI-instruction. By default the channel A and B will receive the same instructions in write mode. In read mode only A is active. ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface ...
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Table 17. Register allocation map [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 ADC control register 0003 Channel index R 0005 Reset and R/W SW_RST - ...
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Table 17. Register allocation map …continued [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 0821 Cfg_1_BID R/ 0822 Cfg_3_SCR_L R/W* SCR 0 0823 Cfg_4_F R/W* 0 ...
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Table 17. Register allocation map …continued [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 0870 LaneA_0_Ctrl R/W 0 SCR_IN_ MODE 0871 LaneB_0_Ctrl R/W 0 SCR_IN_ MODE 0890 ADCA_0_Ctrl ...
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... DIFF_SE R CLKDIV2_SEL R/W 0 DCS_EN R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 111111 not used ADCB will get the next SPI command: 0 ADCB not selected 1 ADCB selected ADCA will get the next SPI command: 0 ADCA not selected 1 ADCA selected ...
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... TESTPAT_1[2:0] R/W Table 24. Register test pattern 2 (address 0015h) Bit Symbol Access TESTPAT_2[13:6] R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 0000 not used enable internal programmable VREF mode: 0 disable 1 active programmable internal reference: 000 0 dB (FS=2 V) −1 dB (FS=1.78 V) 001 − ...
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... Symbol Access 7 SW_RST R FSM_SW_RST R ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 00000 custom digital test pattern (bit 000 not used Value Description 0 set to 1 when a synchronization error occurs 100 reserved 0 not used 1 power-on-reset ...
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... R 6 TRISTATE_CFG_PAD R/W 5 SYNC_POL R/W 4 SYNC_SINGLE_ENDED R ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface [1] Value Description 0000 not used 0000 defines quick JESD204A configuration. These settings overrule the (reset) CFG_PAD configuration 0000 ADC0: ON; ADC1: ON; Lane0: ON; Lane1 0001 ADC0: ON ...
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... SER scramblerB (address 080Ah) Bit Symbol Access MSB_INIT[7:0] R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface …continued Value Description enables swapping bits at the scrambler input 0 1 LSB are swapped to MSB at the scrambler input enables swapping bits at the 8b/10b encoder input: ...
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... K[4:0] R/W Table 40. Cfg_6_M (address 0825h) Bit Symbol Access R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 000000 not used defines the type of Pseudo-Random Binary Sequence (PRBS) generator to be used: 00 (reset) PRBS-7 01 PRBS-7 10 PRBS-23 11 PRBS-31 Value ...
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... LID[4:0] R/W Table 47. Cfg02_13_fchk (address 084Ch) Bit Symbol Access FCHK[7:0] R ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 0 not used * defines the number of control bits per sample, minus 1 00 not used **** defines the converter resolution Value Description ...
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... Bit Symbol Access SCR_IN_MODE R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description ******** defines the checksum value for lane1 checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in JEDEC Standard No.204A) Value Description 0 not used ...
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... ADC_MODE[1:0] R ADC_PD R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface …continued Value Description defines output type of lane output unit: 00 (reset) normal mode: Lane output is the 8b/10b output unit 01 constant mode: Lane output is set to a constant (0x0) 10 toggle mode: Lane output is toggling between 0x0 and 0x1 ...
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... ADC_MODE[1:0] R ADC_PD R/W ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Value Description 00 not used defines input type of JESD204A unit 00 (reset) ADC output is connected to the JESD204A input 01 not used 10 JESD204A input is fed with a dummy constant, set to: OTR = 0 and ADC[13:0] = “10011011101010” ...
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... Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version IEC SOT684 Fig 24. Package outline SOT684-1 (HVQFN56) ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface 1 1 ...
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... ADC1413D_SER_4 20100423 Modifications: Product status changed from Objective to Preliminary ADC1413D_SER_3 20100412 ADC1413D065_080_105_125_2 20090604 ADC1413D065_080_105_125_1 20090528 ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface Data sheet status Change notice Preliminary data sheet - Objective data sheet - Objective data sheet - Objective data sheet - All information provided in this document is subject to legal disclaimers ...
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... ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... For sales office addresses, please send an email to: ADC1413D_SER_4 Preliminary data sheet ADC1413D series; serial JESD204A interface NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Register description . . . . . . . . . . . . . . . . . . . . 29 13.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 29 13.6.4 JESD204A digital control registers . . . . . . . . . 31 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 ADC1413D series; serial JESD204A interface 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 17 Contact information . . . . . . . . . . . . . . . . . . . . 42 18 Contents I(cm) Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...