ADC1413D NXP Semiconductors, ADC1413D Datasheet - Page 21

• Manufacturer Part Number: ADC1413D
• Description: Dual 14-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1413D_SER_4
Preliminary data sheet
13.3.3 Duty cycle stabilizer
13.3.4 Clock input divider
13.4.1 Serial output equivalent circuit
13.4 Digital outputs
If single-ended is implemented without setting SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = 1; see
30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the
input clock signal should have a duty cycle of between 45 % and 55 %.
Table 12.
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
The JESD204A standard specify that in case of connecting the receiver and the
transmitter in DC coupling, both of them need to be provided by the same supply.
The output should be terminated when 100 Ω (typical) has been reached at the receiver
side.
DCS_enable SPI
0
1
Fig 19. CML output connection to the receiver in DC coupling
Duty cycle stabilizer
All information provided in this document is subject to legal disclaimers.
+
Table
Rev. 04 — 23 April 2010
20), the circuit can handle signals with duty cycles of between
12 mA to 26 mA
Table
50 Ω
−
20). This feature allows the user to deliver a higher
VDDD
CMLPA/CLMPB
CMLNA/CLMNB
AGND
ADC1413D series; serial JESD204A interface
Description
duty cycle stabilizer disable
duty cycle stabilizer enable
ADC1413D series
100 Ω
RECEIVER
005aaa082
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