MPC89L51A Megawin Technology, MPC89L51A Datasheet - Page 28

• Manufacturer Part Number: MPC89L51A
• Description: 8-bit micro-controller
• Manufacturer: Megawin Technology

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MPC89x51A carried with convenient mechanism to help the user read/change the flash content.
Just filling the target address and data into several SFR, and triggering the built-in ISP
automation, the user can easily erase, read, and program the embedded flash and option
registers OR1.
There are several SFR designed to help the user implement the ISP functionality.
SFR: IFD (ISP Flash Data register):
SFR: IFADRH (ISP Flash Address High):
SFR: IFADRL (ISP Flash Address Low):
SFR: IFMT (ISP Flash Mode Table):
SFR: SCMD (Sequential Command Data register for ISP) :
Note: OR0 cannot be changed by ISP operation. It can be accessed only by Writer. Only OR1 can be
IFD is the data port register for ISP operation. The data in IFD will be written into the desired address in
operating ISP write and it is the data window of readout in operating ISP read.
IFADRH is the high-bytes address port for all ISP modes.
IFADRL is the low-bytes address port for all ISP modes.
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Bits-7
Bits-7
Bits-7
Bits-7
Mode Selection
changed by ISP program.
1
0
0
0
0
1
1
1
0
0
1
1
0
1
Bits-6
Bits-6
Bits-6
Bits-6
(High bytes of the address pointing to flash memory)
(Low bytes of the address pointing to flash memory)
(Data to be written into flash, or data got from flash)
0
1
0
1
1
0
1
reserved
Bits-5
Bits-5
Bits-5
Bits-5
Standby
AP-memory read
AP-memory/Data-flash program
AP-memory/Data-flash page erase
OR1 memory erase (IFADRL[0]=1).
OR1 memory read ( IFADRL[0] =1)
OR1 memory program ( IFADRL[0] = 1)
MPC89x51A Data Sheet
Bits-4
Bits-4
Bits-4
Bits-4
Bits-3
Bits-3
Bits-3
Bits-3
To Operate
Bits-2
Bits-2
Bits-2
Bits-2
Mode Selection
Bits-1
Bits-1
Bits-1
Bits-1
Bits-0
Bits-0
Bits-0
Bits-0
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