MPC8358E Freescale Semiconductor, MPC8358E Datasheet - Page 39

• Manufacturer Part Number: MPC8358E
• Description: (MPC8358E / MPC8360E) PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
• Manufacturer: Freescale Semiconductor

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Figure 20
8.3.3
Table 38
Freescale Semiconductor
At recommended operating conditions with LVDD is 3.3 V ± 10%
Timer clock cycle time
Input Setup to timer clock
Input Hold from timer clock
Output clock to output valid
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk
(reference)(state)
t
outputs (D) are invalid (X) or data hold time. Also, t
to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz).
of 300 MHz, the delay is 63 ns).
MDKHDX
provides the IEEE Std. 1588 timer AC specifications.
shows the MII management AC timing diagram.
Parameter/Condition
IEEE Std. 1588™ Timer AC Specifications
symbolizes management data timing (MD) for the time t
(Output)
(Input)
for inputs and t
MDIO
MDIO
MDC
Parameter
Table 37. MII Management AC Timing Specifications (continued)
Figure 20. MII Management Interface Timing Diagram
(first two letters of functional block)(reference)(state)(signal)(state)
t
MDCH
Table 38. 1588 Timer AC Specifications
t
MDRDVKH
Symbol
t
MDC
t
t
MDHF
MDTKHDX
1
MDRDVKH
Min
—
t
t
Symbol
t
t
TMRCKS
TMRCKH
t
GCLKNV
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
TMRCK
MDHF
symbolizes management data timing (MD) with respect
MDC
t
MDRDXKH
Typ
from clock reference (K) high (H) until data
—
t
MDCR
(first two letters of functional block)(signal)(state)
MDC
Min
—
—
0
0
clock reference (K) going to the high
for outputs. For example,
Max
10
Max
70
—
—
6
Unit
ns
MHz
Unit
—
—
ns
Notes
Notes
2,3
2,3
1
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