MPC8358E Freescale Semiconductor, MPC8358E Datasheet - Page 34

• Manufacturer Part Number: MPC8358E
• Description: (MPC8358E / MPC8360E) PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
• Manufacturer: Freescale Semiconductor

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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 16
8.2.4
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
Table 33
34
At recommended operating conditions with LV
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TBI data TCG[9:0] delay
GTX_CLK clock rise time, VIL(min) to VIH(max)
GTX_CLK clock fall time, VIH(max) to VIL(min)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
3. In rev 2.0 silicon, due to errata, t
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
)(reference)(state)
symbolizes the TBI transmit timing (TT) with respect to the time from t
signals (D) reach the valid state (V) or setup time. Also, t
the time from t
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t
convention is used with the appropriate letter: R (rise) or F (fall).
document.
provides the TBI transmit AC timing specifications.
shows the RMII receive AC timing diagram.
TBI AC Timing Specifications
TBI Transmit AC Timing Specifications
Parameter/Condition
REF_CLK
TTX
RXD[1:0]
CRS_DV
for inputs and t
RX_ER
(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note
Table 33. TBI Transmit AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDX
Figure 16. RMII Receive AC Timing Diagram
t
RMRDVKH
t
RMXH
DD
/ OV
minimum is 0.7 ns for UCC1. Please refer to QE_ENET19 in the device errata
TTX
t
RMX
DD
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
of 3.3 V ± 10%.
Valid Data
t
G125H
t
TTKHDX
Symbol
TTXH
t
t
TTKHDX
TTKHDV
t
t
t
t
TTXR
TTXF
G125
t
TTX
RMXF
/t
/t
TTX
G125
symbolizes the TBI transmit timing (TT) with respect to
1
TTX
(first two letters of functional block)(signal)(state
t
RMRDXKH
(K) going high (H) until the referenced data
t
Min
1.0
RMXR
40
45
—
—
—
—
—
for outputs. For example, t
Typ
8.0
8.0
—
—
—
—
—
Max
5.0
1.0
1.0
60
55
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
%
TTKHDV
Notes
3
2