MT9040 Zarlink Semiconductor, MT9040 Datasheet - Page 5

• Manufacturer Part Number: MT9040
• Manufacturer: Zarlink Semiconductor

Four tapped delay lines are used to generate
16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz
signals.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and five frame pulse
outputs. The C8o, C4o and C2o clocks are generated
by simply dividing the C16o clock by two, four and
eight respectively. These outputs have a nominal
50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal
to generate the C1.5o clock by dividing the internal
C12 clock by eight. This output has a nominal 50%
duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal
to generate the clock output C6o. This output has a
nominal 50% duty cycle.
The frame pulse outputs (F0o, F8o, F16o, TSP, and
RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, all frame pulse
and clock outputs are locked to one another for all
operating states, and are also locked to the input
reference in Normal Mode. See Figures 9,10 and 11.
DPLL
From
Figure 4 - Output Interface Circuit Block
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Delay
Line
Line
Line
Line
Diagram
12MHz
16MHz
19MHz
12MHz
E1 Divider
DS2 Divider
T1 Divider
C19o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
C6o
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for
a complete loss of incoming signal, or a large
frequency shift in the incoming signal. If the input
signal is outside the Impairment Monitor Capture
Range the PLL automatically changes from Normal
Mode to Free Run Mode. See AC Electrical
Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal
returns to normal, the DPLL is returned to Normal
Mode.
Master Clock
The MT9040 can use either a clock or crystal as the
master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.
Control and Mode of Operation
The MT9040 has two possible modes of operation,
Normal and Freerun. As shown in Table 2, the Mode/
Control Select pin MS selects the mode.
Normal Mode
Normal Mode is typically used when a slave clock
source, synchronized to the network is required.
In Normal Mode, the MT9040 provides timing (C1.5o,
C2o, C4o, C8o, C16o and C19o) and frame
synchronization (F0o, F8o, F16o, TSP and RSP)
signals, which are synchronized to the reference
input. The input reference signal may have a nominal
frequency
19.44MHz.
From a reset condition, the MT9040 will take up to 30
seconds (see AC Electrical Characteristics) of input
reference signal to output signals which are
synchronized (phase locked) to the reference input.
MS
0
1
Table 2 - Operating Modes and States
Advance Information
of
8kHz,
1.544MHz,
FREERUN
NORMAL
Mode
2.048MHz
MT9040
or
5