MT9040 Zarlink Semiconductor, MT9040 Datasheet

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MT9040

Manufacturer Part Number
MT9040
Description
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Applications
Supports AT&T TR62411 and Bellcore GR-
1244-CORE and Stratum 4 timing for DS1
interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
JTAG Boundary Scan
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse source
TRST
TMS
TDO
TCK
REF
TDI
OSCi
Master Clock
1149.1a
IEEE
Control State Machine
MS
OSCo
RST
Figure 1 - Functional Block Diagram
IM
FLOCK
LOCK
Impairment
DS5406
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides
timing and synchronization signals for T1 and E1
primary rate transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and
capture range for these specifications.
Monitor
DPLL
Input
Feedback
VDD
MT9040AN
VSS
FS1
Frequency
Interface
Output
Select
Circuit
MUX
Ordering Information
-40 to +85 ° C
FS2
ISSUE 2
T1/E1 Synchronizer
Advance Information
48 Pin SSOP
MT9040
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
January 2001
1

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MT9040 Summary of contents

Page 1

... The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9040 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy and capture range for these specifi ...

Page 2

... RST Reset (Input). A logic low at this input resets the MT9040. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs are at logic high ...

Page 3

... Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test- Logic-Reset state. 47 TCK Test Clock (Input). Provides the clock to the JTAG test logic. 48 TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. Advance Information Description . DD MT9040 3 ...

Page 4

... Table 1 - Input Frequency Selection Digital Phase Lock Loop (DPLL) As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled Oscillator and a Control Circuit. Phase Detector - the Phase Detector compares the reference signal with the feedback signal from the ...

Page 5

... The input reference signal may have a nominal frequency of 8kHz, 19.44MHz. From a reset condition, the MT9040 will take seconds (see AC Electrical Characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. MT9040 Mode ...

Page 6

... Table 1. Fast Lock Mode Fast Lock Mode is a submode of Normal Mode used to allow the MT9040 to lock to a reference more quickly than Normal mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is set high. ...

Page 7

... Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9040, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. Capture Range Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization ...

Page 8

... Master Clock The MT9040 can use either a clock or crystal as the master timing source. In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the OSCi pin. For applications not ...

Page 9

... RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns. MT9040 +3.3V R 10kΩ RST R P 1kΩ Figure 7 - Power-Up Reset Circuit Advance Information Ω Ω for P C 10nF MT9040 9 ...

Page 10

... MT9040 Advance Information Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 48 SSOP package power dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Characteristics 1 Supply voltage ...

Page 11

... Min ±0ppm -0 ±32ppm -32 ±100ppm -100 ±0ppm -230 ±32ppm -198 ±100ppm -130 -18k 1.544MHz -36k 2.048MHz -36k Sym Timing Reference Points t MT9040 Conditions/ Max Units Notes† +0 ppm 4-8 +32 ppm 4-8 +100 ppm 4-8 +230 ppm 1-3,5-8 +198 ppm 1-3,5-8 +130 ppm 1-3,5 1-3,5-14 +18k ...

Page 12

... MT9040 Advance Information AC Electrical Characteristics - Input/Output Timing Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference input to F8o delay 6 19.44MHz reference input to F8o delay 7 F8o to F0o delay ...

Page 13

... C19WL C19o Advance Information R15D R2D F0WL t F16WL t F16S t C8W t C4W t C2W t C6W t C6W t C15W t C19WH Figure 10 - Output Timing 1 MT9040 t R8D R19D F8WH F0D F16H t C16D C8D C4D V T ...

Page 14

... MT9040 Advance Information F8o C2o RSP TSP F8o MS1,2, RSEL, PCCi Figure 12 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic jitter at F16o (8kHz) 4 Intrinsic jitter at C1.5o (1.544MHz) 5 Intrinsic jitter at C2o (2.048MHz) 6 Intrinsic jitter at C6o (6 ...

Page 15

... UIpp Sym Min Max Units 0.015 UIpp 0.010 UIpp 0.010 UIpp 0.005 UIpp Sym Min Max Units MT9040 Conditions/Notes† 1-12,19-22,27 1-12,19-22,27 1-12,19-22,27 1-12,19-22,27 Conditions/Notes† 1-12,19-22,28 1-12,19-22,28 1-12,19-22,28 1-12,19-22,28 Conditions/Notes† 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26 ...

Page 16

... MT9040 Advance Information AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer Characteristics 1 Jitter attenuation for 1Hz@20UIpp input 2 Jitter attenuation for 1Hz@104UIpp input 3 Jitter attenuation for 10Hz@20UIpp input 4 Jitter attenuation for 60Hz@20UIpp input 5 Jitter attenuation for 300Hz@20UIpp input 6 Jitter attenuation for 10kHz@0.3UIpp input 7 Jitter attenuation for 100kHz@0 ...

Page 17

... UIpp 1,3,7 -12,19-20,22-24,26 0.01 UIpp 1,3,7 -12,19-20,22-24,26 Sym Min Max Units 150 UIpp 140 UIpp 130 UIpp 35 UIpp 25 UIpp 15 UIpp 4 UIpp 1 UIpp 0.5 UIpp Sym Min Max Units 150 UIpp 140 UIpp 130 UIpp 50 UIpp 40 UIpp 20 UIpp 5 UIpp 1 UIpp 1 UIpp MT9040 Conditions/Notes† Conditions/Notes† 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 Conditions/Notes† 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 1,5,7 -12,19-20,22-24,28 17 ...

Page 18

... MT9040 Advance Information AC Electrical Characteristics - OSCi 20MHz Master Clock Input Characteristics 1 Tolerance Duty cycle 5 Rise time 6 Fall time † See "Notes" following AC Electrical Characteristics tables. † Notes: Voltages are with respect to ground (V ) unless otherwise stated. SS Supply voltage and operating temperature are as per Recommended Operating Conditions. ...

Page 19

Small Shrink Outline Package (SSOP Suffix Pin Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin 5) A ...

Page 20

... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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