MT9040 Zarlink Semiconductor, MT9040 Datasheet - Page 3

• Manufacturer Part Number: MT9040
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
33,34,
37, 39
Pin #
14
15
16
18
19
20
21
22
24
25
26
27
29
30
32
42
36
40
41
44
45
46
47
48
FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less
Name
C1.5o
LOCK
TRST
C16o
C19o
TDO
TMS
TSP
TCK
C2o
C4o
C8o
C6o
FS2
FS1
F8o
TDI
NC
MS
IM
IC
IC
IC
IC
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 11.
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 10.
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and
4.096Mb/s.
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
than 500 ms locking time).
Internal Connection. Tie low for normal operation.
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384MHz clock.
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
Internal Connection. Tie high for normal operation.
No Connection. Leave open circuit .
Internal Connection. Tie low for normal operation.
Mode/Control Select (Input). This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
Internal Connection. Tie low for normal operation.
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See
Table 1.
Frequency Select 1 (Input). See pin description for FS2.
Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-
Logic-Reset state.
Test Clock (Input). Provides the clock to the JTAG test logic.
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller.
DD
.
Description
Advance Information
MT9040
3