MT9040 Zarlink Semiconductor, MT9040 Datasheet - Page 4

• Manufacturer Part Number: MT9040
• Manufacturer: Zarlink Semiconductor

MT9040
Functional Description
The MT9040 is a T1/E1 Trunk Synchronizer,
providing timing (clock) and synchronization (frame)
signals to interface circuits for T1 and E1 Primary
Rate Digital Transmission links. Figure 1 is a
functional block diagram which is described in the
following sections.
Frequency Select MUX Circuit
The MT9040 operates on the falling edge of the
reference. It operates with one of four possible input
reference frequencies (8kHz, 1.544MHz, 2.048MHz
or 19.44MHz). The frequency select inputs (FS1 and
FS2) determine which of the four frequencies may be
used at the reference input. A reset (RST) must be
performed after every frequency select input change.
See Table 1.
Digital Phase Lock Loop (DPLL)
As shown in Figure 3, the DPLL of the MT9040
consists of a Phase Detector, Loop Filter, Digitally
Controlled Oscillator and a Control Circuit.
Phase Detector - the Phase Detector compares the
reference signal with the feedback signal from the
Frequency Select MUX circuit, and provides an error
signal
between the two. This error signal is passed to the
Loop Filter. The Frequency Select MUX allows the
proper feedback signal to be externally selected
(e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
4
FS2
0
0
1
1
Table 1 - Input Frequency Selection
corresponding
Reference
FS1
0
1
0
1
Advance Information
Frequency Select MUX
Feedback Signal
to
Detector
Phase
from
Input Frequency
the
19.44MHz
1.544MHz
2.048MHz
phase
8kHz
Figure 3 - DPLL Block Diagram
difference
Input Impairment Monitor
State Select
State Machine
from
State Select
Loop Filter
from
Loop Filter - the Loop Filter is similar to a first order
low pass filter with a 1.9 Hz cutoff frequency for all
four
1.544MHz, 2.048MHz or 19.44MHz). This filter
ensures that the network jitter transfer requirements
are met.
Control Circuit - the Control Circuit uses status and
control information from the State Machine and the
Input Impairment Circuit to set the mode of the
DPLL. The two possible modes are Normal and
Freerun.
Digitally Controlled Oscillator (DCO) - the DCO
receives the filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital
output signal. The synchronization method of the
DCO is dependent on the state of the MT9040.
In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the input
reference signal.
In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.
Lock Indicator - If the PLL is in frequency lock
(frequency lock means the center frequency of the
PLL is identical to the line frequency), and the input
phase offset is small, then the lock signal will be set
high.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 4. The Output Interface Circuit uses four
Tapped Delay Lines followed by a T1 Divider Circuit,
an E1 Divider Circuit, and a DS2 Divider Circuit to
generate the required output signals.
reference
Controlled
Oscillator
Digitally
Control
Circuit
frequency
Output Interface Circuit
DPLL Reference
selections
to
(8kHz,