MT90210 Zarlink Semiconductor, MT90210 Datasheet - Page 17

• Manufacturer Part Number: MT90210
• Description: 3072 Channels TDM to Dual Port RAM Multiple Rate Parallel Bus Access Circuit (MRPAC)
• Manufacturer: Zarlink Semiconductor

MT90210
C = channel number, S = stream number
2-160
4 or 5 (@ 8 M)
4 or 5 (@ 2M)
4 or 5 (@ 2M)
4 or 5 (@ 8M)
STROBE
2M ts
8M ts
P7:P0
RBC
WBC
R/W1
R/W2
Mode
1
1
2
2
3
3
Finished reading last channel of 8Mb/s
and 4
ch 124
th
quarter of last channel of 2 Mb/s of one complete frame(125 us)
Table 5 - Memory Address Location Formulae for all modes of operation
TX/RX
3 channel delay for 8 Mb/s rate
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
ch 125
Frame n, channel 31
Figure 13 - Mode 4 and Mode 5 Read/Write Timing
Memory Address Location Formula
ch 126
8C + (S-16) + 0C00h
8C + (S-16) + 0400h
24C + S + 0400h
24C + S + 0800h
12C + S + 0800h
16C + S + 0800h
for Block 0
24C + S
24C + S
12C + S
16C + S
ch 127
ch 0
Finished writing last channel of 8 Mb/s
and 4
th
quarter of last channel of 2 Mb/s
Memory Address Location Formula
Frame n+1, channel 0
"a" denotes data for S0-S3
"b" denotes data for S4-S7
"c" denotes data for S8-S11
"d" denotes data for S12-S15
ch 1
8C + (S-16) + 1C00h
8C + (S-16) + 1400h
24C + S + 1000h
24C + S + 1800h
12C + S + 1000h
12C + S + 1800h
16C + S + 1000h
16C + S + 1800h
24C + S + C00h
24C + S + 800h
for Block 1
ch 2
ch 3