MT90210 Zarlink Semiconductor, MT90210 Datasheet - Page 11

• Manufacturer Part Number: MT90210
• Description: 3072 Channels TDM to Dual Port RAM Multiple Rate Parallel Bus Access Circuit (MRPAC)
• Manufacturer: Zarlink Semiconductor

Instruction Register
In accordance with the IEEE 1149.1 standard, the
MT90210 uses public instructions listed in Table 1.
The MT90210 JTAG Interface contains a two bit
instruction register. Instructions are serially loaded
into the Instruction Register from the TDI when the
TAP Controller is in its Shift-IR state. Subsequently,
the instructions are decoded to achieve two basic
functions: to select the test data register that may
operate while the instruction is current and to define
the serial test data register path that is used to shift
data between TDI and TDO during data register
scanning.
Test Data Registers
As specified in the IEEE 1149.1 Standard, the
MT90210 JTAG interface contains two test data
registers:
•
•
The MT90210 boundary-scan register contains 144
bits. Bit 144 in Table 2 is the first bit clocked out. All
tristate enable bits are asserted high: a logic 1
enables
outputs/bidirectionals. Note that clocking all zeros
into the scan path register will set all outputs to
tristate.
MT90210
2-154
[00]
[01],
[10]
[11]
I[0:1] Instruction
The Boundary Scan Register
The Bypass Register
EXTEST
SAMPLE/
PRELOAD
BYPASS/
NOTEST
the
corresponding
Boundary-Scan
register selected,
Test Enabled
Boundary-Scan
register selected,
Test Disabled
Bypass register
selected,
Test Disabled
This instruction is specifically provided to allow board-level interconnect
testing of opens, bridging errors etc.
When the EXTEST instruction is selected, the on-chip logic is isolated
from the MT90210’s I/O pin such that the value of the I/O pins is
determined by its boundary-scan register. Data for the execution of this
instruction can be preloaded into the boundary-scan register with the
SAMPLE/PRELOAD instruction.
Two functions can be performed by the use of this instruction. It allows a
SAMPLE (‘snapshot’) of the normal operation of the MT90210 to be
taken for examination. And, prior to the selection of another test
operation, a PRELOAD can place data values into the latched parallel
outputs of the Boundary-Scan cells. During the execution of the
instruction, the on-chip logic operation is not hampered in any way.
This instruction is used to BYPASS the MT90210 while performing
boundary-scan testing on other devices with scan registers in the same
serial register chain. The MT90210 is allowed to function normally. This
instruction is automatically loaded upon reset of the MT90210, as
specified in IEEE1149.1
Table1 - Instruction Register
group
of
†
Description
101:102
103:128
129:130
131:132
133:144
77:100
B - bidirectional: input cell, output cell followed by
I - input: input cell.
O - output: output cell, followed by tristate cell.
66:68
71:72
73:76
Bits
1:60
tristate cell.
61
62
63
64
65
69
70
Table 2 - Boundary Scan Register
R/W1 - R/W2
MD2 - MD0
Definition
S4 - S23
A0 - A12
P0 - P7
S0 - S3
Strobe
OEser
SCLK
PCLK
RDIN
WBC
CKO
RBC
HC4
RST
F0i
BSC Type
B
O
O
B
O
O
O
O
B
I
I
I
I
I
I
I
I
†