MT90210 Zarlink Semiconductor, MT90210 Datasheet - Page 10

• Manufacturer Part Number: MT90210
• Description: 3072 Channels TDM to Dual Port RAM Multiple Rate Parallel Bus Access Circuit (MRPAC)
• Manufacturer: Zarlink Semiconductor

JTAG Support
The MT90210 JTAG interface is designed according
to the Boundary-Scan standard IEEE1149.1. The
standard specifies a design-for-testability technique
called Boundary-Scan Test (BST). A boundary-scan
IC has a shift-register stage or ‘Boundary-Scan Cell’
(BSC) in between the core logic and the I/O buffers
adjacent to each I/O pin. The BSCs can control and
observe what happens at each I/O pin of the IC. The
operation of the boundary-scan circuitry is controlled
by a Test Access Port (TAP) Controller.
Note: The MT90210 device performs groups of writes and groups of reads separated by 4 inactive PCLK periods
Figure 7b - WBC and RBC operation in relation to accessing data from Block 0 and Block 1
RBC
WBC
for modes 3, 4 and 5. In mode 1 and mode 2, the write and read groups are separated by 8 PCLK periods.
SCLK
PCLK
A0-A12
R/W1
R/W2
Strobe
P0-P7
Exclusive access of
Block 0
Figure 8 - Parallel Port Functional Read/Write Operation
125 us
A
RD
RD
A
RD
RD
Access
Block 0
Block 1
of both
t
NA
&
Exclusive access of
125 us
Block 1
Test Access Port (TAP)
The Test Access Port (TAP) provides access to many
test support functions built into the MT90210. It
consists of three input connections and one output
connection. The following connections form the TAP:
•
•
•
•
•
Test Clock Input (TCK)
Test Mode Select Input (TMS)
Test Data Input (TDI)
Test port Reset (TRST)
Test Data Output (TDO)
Access
Block 0
Block 1
A
of both
WR
t
t
t
WR
&
NA
NA
NA
~ 1 timeslot for modes 1, 2 & 3
~ 3 timeslots for modes 4 & 5
A
WR
WR
Exclusive access of
Block 0
Toggles only during
Changes state (high to low)
on every change of a block
of reads or block of writes
Low during read cycle,
high during inactive
periods and toggles
during write cycles
write data cycle
MT90210
2-153