MT90210 Zarlink Semiconductor, MT90210 Datasheet
MT90210
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MT90210 Summary of contents
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... Scan Test Multi-Rate Parallel Access Circuit DS5026 MT90210AL Description The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability ...
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... TDO Boundary Scan Test Data Output. 29 RDin Read P0-P7 input clock . This input is used by the MT90210 to sample bytes coming in at the parallel port P0-P7 lines. Typically, the user should connect CKout to this input. 30 OEser Serial Port Output Enable (Input). On the parallel-to serial conversion direction, this input is used by the MT90210 to know which time-slots on the serial output streams will be placed in high-impedance ...
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... MD2-0=000), 4.096 (mode 2, MD2-0=001) or 8.192 (mode 3, MD2-0=010) Mb/s data rates are available. When MD2-0 are set to 011 (mode 4), the MT90210 operates in mixed data rates mode where S16-23 operate at 8.192 Mb/s and the remaining serial streams run at 2.048 Mb/s. In mode 5 (MD2-0=100), the MT90210 operates as per mode 4 but the device will accept a differential clock reference at 16 ...
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... Once WBC toggles, the local CPU can access the Dual port memory to get the data while the MT90210 writes the contents of the next 125 µ s frame into the other half (addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125 µ s. When this signal is low, the MT90210 is writing to the lower memory block ...
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... MT90210 reads or writes the complementary frame in the memory. For example, in mode 3 (Figure 4), during the first frame the MT90210 will read and write in to the first half of the memory space (Block 0) and during the second frame the MT90210 will read and write in to the second half of the memory space (Block 1) ...
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... Address outputs used: A0-A12 Legend: unused memory space Figure 4 - Dual Port RAM Memory Map for Mode 4: The MT90210 is configured such that the 24 serial streams are bidirectional and split into two different functional groups: (i) streams S0-S15 operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23 operate at 8 ...
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... Figure 13. The MT90210 device repeats the same sequence of operation as shown in Table 4 throughout the entire frame. In mode 4 and mode 5 the MT90210 device is configured with 24 bidirectional serial streams and split into two different rates S15 operate at 2.048 Mb/s data rates (512 time-slots) and streams S16 to S23 run at 8 Mb/s data rates (1024 time-slots) ...
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... Data inactive Out MT90210 will handle parallel por transactions related to frame n +1. address y inactive Data inactive In MT90210 will handle parallel port transactions related to frame n +1. Ch. 0, Bit 6 Ch. 0, Bit 6 Ch. 0, Bit 5 Ch. 0, Ch. 0, Ch. 0, Ch. 0, Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Strobe P0-P7 RD Note: The MT90210 device performs groups of writes and groups of reads separated by 4 inactive PCLK periods for modes 3, 4 and 5. In mode 1 and mode 2, the write and read groups are separated by 8 PCLK periods. Figure 8 - Parallel Port Functional Read/Write Operation JTAG Support The MT90210 JTAG interface is designed according to the Boundary-Scan standard IEEE1149 ...
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... When the EXTEST instruction is selected, the on-chip logic is isolated from the MT90210’s I/O pin such that the value of the I/O pins is determined by its boundary-scan register. Data for the execution of this instruction can be preloaded into the boundary-scan register with the SAMPLE/PRELOAD instruction ...
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... PLLAGND LP1 LP2 * Note: Dual Port RAM: Cypress part number: CY7B145-15 and IDT part number IDT7015 Figure 9 - Functional Example of the MT90210 Application Circuit Applications The MT90210 device may be used in applications such as video and teleconferencing bridge cards and voice processing cards for CTI (Computer Telephony Integration) ...
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... C1= 10nF + 5% C2= 20pF Figure 10 - Analog PLL Low Pass Filter Circuit PLL Considerations The MT90210 device contains an analog Phase- Locked Loop (PLL) which is used to create a higher speed clock for parallel port operation from the input SCLK. This analog PLL requires a loop filter circuit to ...
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... INACTIVE MT90210 Memory Address 0DE8h 0DE9h 0DEAh 0DEBh 0DECh 0DEDh 0DEEh 0DEFh 0DF0h 0DF1h 0DF2h 0DF3h 1000h 1001h 1002h 1003h 1004h 1005h 1006h 1007h 1008h 1009h 100Ah 100Bh 2-157 ...
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... MT90210 PCLK Cycle Read Write 104 ...
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... S23-S0 frame n, nd channel 0 2 last channel Finished reading last channel of frame n RBC WBC R/W1 R/W2 STROBE Figure 12 - Modes Read/Write Timing Frame n+1, channel 0 Write data from S23-S0 frame n, last channel Finished writing last channel of frame n MT90210 Read data for S23-S0 frame n+1, channel 1 2-159 ...
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... MT90210 2M ts Frame n, channel 124 ch 125 3 channel delay for 8 Mb/s rate P7:P0 Finished reading last channel of 8Mb/s th and 4 quarter of last channel of 2 Mb/s of one complete frame(125 us) RBC WBC R/W1 R/W2 STROBE Figure 13 - Mode 4 and Mode 5 Read/Write Timing Memory Address Location Formula Mode TX/ ...
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... Typ T - 4.75 5.0 DD † Sym Min Typ 2 MT90210 Min Max Units 6 V +0 unless otherwise stated SS Max Units Test Conditions °C +85 5.25 V Max Units Test Conditions 100 0 ...
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... MT90210 AC Electrical Characteristics timing specifications. The setup/hold and propagation delays are based on a single reference level which is 1.5V for TTL(V CMOS ( Voltage Value when Voltage Reference Connected to TTL not applicable CT t Clock Input Data 2-162 † ...
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... Mode 1, last channel = 31 Mode 2, last channel = 63 Mode 3, last channel = 127 Figure 18 - Serial Port Timing for Modes Figure 17 - Output Delays t frw t frh t frs t clk t clkl t clkh t stis † bit 7, ch.0 t stod bit 7, ch.0 † MT90210 stih 2-163 ...
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... MT90210 F0i (8kHz) S0-15 bit 0, ch. 31 (2.048 Mb/s) (inputs) S0-15 bit 0, ch. 31 (2.048 Mb/s) (outputs) t HC4 hclkl (4.096 MHz) t clkl (16.384 MHz) t clkh t clk S16-S23 (8.192 Mb/s) (inputs) S16-S23 bit 1, ch. 127 (8.192 Mb/s) (outputs) Figure 19 - Serial Port Timing for Modes 4 and 5 SCLK, C16+ S0-23 S0-23 2-164 t hfrw t t frs ...
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... MT90210 Max Units Test Conditions =1K, C =200pF ...
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... MT90210 CKout (mode 3/4/5) t dpll SCLK C16+ C16 - SCLK or C16+, C16- CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/ A0-A12 X RDin input t st P0-P7 (Read/ X(rd) Write) Strobe t oes Valid OEser input Note: R/W1 output signal is HIGH and R/W2 output signal is LOW during read cycles. Figure 22 - Parallel Port Data Read Cycle ...
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... Sym Min Typ r/wd stb t pwe 13 dod t 2. oes oeh MT90210 S t pwe t pwe Max Units Test Conditions 15 ns output load 50pF 9 pulse width low on PCLK for output load 2-167 ...
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