HY27UA1G1M Hynix Semiconductor, HY27UA1G1M Datasheet - Page 22

• Manufacturer Part Number: HY27UA1G1M
• Description: 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
• Manufacturer: Hynix Semiconductor

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Automatic Page 0 Read Description.
At powerup, once the supply voltage has reached the threshold level, V
state and the internal NAND device functions (reading, writing, erasing) are enabled.
The device then automatically switches to read mode where, as in any read operation, the device is busy for a time
t
High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, RE, signal. Figures 18
and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
Sequential Row Read Disabled
If the device is delivered with Sequential row read disabled Automatic Read Page 0 at Power-up, only the first page
(Page 0) will be automatically read after the power-on sequence. Refer to Figure 18.
Sequential Row Read Enabled
If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enable), the device will
automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc.,
until the last memory location is reached, each new page being accessed after a time t
The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to V
mand. Refer to Figure 19.
Note: (1). V
Rev 0.5 / Oct. 2004
Vccth (1)
BLBH1
Vcc
RB
WE
CLE
RE
CE
ALE
I/O
during the data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal goes
Figure 18. Sequential Row Read Disabled and Automatic Page 0 Read at power-up
CCth
is equal to 2.5V for 3V Power Supply devices.
Busy
tBLBH1
Data
from Address N to Last Byte or Word in Page
N
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Data
N+1
Data Output
Data
N+2
CCth
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
, all digital outputs revert to their reset
BLBH1
.
IH
Data
Last
) or by issuing a co-
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