WM8959 Wolfson Microelectronics Ltd., WM8959 Datasheet - Page 81

• Manufacturer Part Number: WM8959
• Description: Mobile Multimedia DAC with Dual-mode Class AB/D Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

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Pre-Production
PLL LOCK OUTPUT
An internal signal used to indicate the lock status of the PLL can be output to a GPIO pin or used to
trigger an Interrupt event. The polarity of the PLL Lock indication may be controlled by register bit
PLL_LCK_POL. Note that this polarity inversion bit applies to the Interrupt register behaviour only; it
does not affect the direct GPIO output of the PLL Lock function. The associated interrupt event may
be masked or enabled by register bit PLL_LCK_IRQ_ENA. The PLL Lock status bit in the IRQ
Register (R18) may be read at any time or else in response to an Interrupt event. See Table 47 for
more details of the Interrupt function.
If direct output of the PLL Lock status bit is required to the external pins of the WM8959, the following
register settings are required:
The register fields used to configure the PLL Lock GPIO function are described in Table 45.
Table 45 PLL Lock GPIO Control
The PLL Lock function operates according to the following truth table:
Table 46 Truth Table for GPIO Output of PLL Lock function
LOGIC '1' AND LOGIC '0' OUTPUT
The GPIO pins can be programmed to drive a logic high or logic low signal. The following register
settings are required:
REGISTER
ADDRESS
R23 (17h)
R22 (16h)
PLL Lock output
PLL Lock output
•
•
•
•
•
•
•
•
•
•
•
•
•
GPIO1_ENA = 1 (only required if using GPIO1)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
AIF_TRIS = 0
GPIOn_SEL = 0100 for the selected PLL Lock status output pin
GPIOn_PU = 0 for the selected PLL Lock status output pin
GPIOn_PD = 0 for the selected PLL Lock status output pin
GPIO1_ENA = 1 (only required if using GPIO1)
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
AIF_TRIS = 0
GPIOn_SEL = 0010 for each Logic ‘0’ output pin
GPIOn_SEL = 0011 for each Logic ‘1’ output pin
GPIOn_PU = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin
GPIOn_PD = 0 for each Logic ‘0’ or Logic ‘1’ GPIO pin
LABEL
8
8
BIT
PLL_LCK_POL
(rw)
PLL_LCK_IRQ_
ENA
LABEL
VALUE
0
1
0b
0b
DEFAULT
PLL not Locked
PLL Locked
PLL Lock polarity
0 = Non-inverted
1 = Inverted
PLL Lock IRQ Enable
0 = disabled
1 = enabled
DESCRIPTION
DESCRIPTION
PP, May 2008, Rev 3.1
WM8959
81