WM8959 Wolfson Microelectronics Ltd., WM8959 Datasheet - Page 110

• Manufacturer Part Number: WM8959
• Description: Mobile Multimedia DAC with Dual-mode Class AB/D Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8959
w
PLL
The integrated PLL can be used to generate SYSCLK for the WM8959 from a wide range of MCLK
reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input
reference clock can be divided by 2 by setting the register bit PRESCALE.
The PLL frequency ratio R is equal to f
by register fields PLLN and PLLK, where PLLN is an integer (LSB = 1) and PLLK is the fractional
portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field
SDM. De-selection of fractional mode results in lower power consumption.
For PLL stability, input frequencies and divisions must be chosen so that 5 ≤ PLLN ≤ 13. Best
performance is achieved for 7 ≤ N ≤9. Also, the PLL performs best when f
and 100MHz.
If PLLK is regarded as a 16-bit integer (instead of a fractional quantity), then PLLN and PLLK may be
determined as follows:
The PLL Control register settings are described in Table 64.
Table 64 PLL Control
EXAMPLE PLL CALCULATION
To generate 12.288MHz SYSCLK from a 12MHz reference clock:
There is a fixed divide by 4 at the PLL output (see Figure 78) followed by a selectable divide by 2 in
the same path. PLL output f
(MCLK_DIV = 10b) sets the required f
There is a selectable pre-scale (divide MCLK by 2) at the PLL input (f
frequency ratio f
sets the required ratio f
R2 (02h)
R60 (3Ch)
R61 (3Dh)
R62 (3Eh)
REGISTER
ADDRESS
•
•
PLLN = int R
PLLK = int (2
2
/f
1
15
7
6
3:0
7:0
7:0
must be set in the range 5 - 13. Disabling the MCLK pre-scale (PRESCALE = 0b)
BIT
2
16
/f
1
(R - PLLN))
PLL_ENA
(rw)
SDM
PRESCALE
PLLN [3:0]
PLLK [15:8]
PLLK [7:0]
= 8.192.
2
LABEL
should be set in the range 90MHz - 100MHz. Enabling the divide by 2
2
= 4 x 2 x 12.288MHz = 98.304MHz.
2
/f
1
(see Figure 78). This ratio is the real number represented
0
0
0b
8h
31h
26h
DEFAULT
PLL Enable
0 = disabled
1 = enabled
Enable PLL Integer Mode
0 = Integer mode
1 = Fractional mode
Divide MCLK by 2 at PLL input
0 = Divide by 1
1 = Divide by 2
Integer (N) part of PLL frequency ratio.
Fractional (K) part of PLL frequency ratio.
(Most significant bits)
Fractional (K) part of PLL frequency ratio.
(Least significant bits)
DESCRIPTION
1
- see Figure 75). The PLL
2
PP, May 2008, Rev 3.1
is set between 90MHz
Pre-Production
110