ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 82

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

6.5.2
30
ATtiny24/44/84
CLKPR – Clock Prescale Register
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range.
To ensure stable operation of the MCU the calibration value should be changed in small. A vari-
ation in frequency of more than 2% from one cycle to the next can lead to unpredicatble
behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to
ensure that the MCU is kept in Reset during such changes in the clock frequency
Table 6-10.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 6-11 on page
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Bit
0x26 (0x46)
Read/Write
Initial Value
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
OSCCAL Value
CLKPR to zero.
0x3F
0x7F
0x00
Internal RC Oscillator Frequency Range
CLKPCE
R/W
7
0
31.
with Respect to Nominal Frequency
Typical Lowest Frequency
R
6
–
0
100%
R
5
–
0
50%
75%
R
4
–
0
CLKPS3
R/W
3
with Respect to Nominal Frequency
CLKPS2
See Bit Description
R/W
2
Typical Highest Frequency
CLKPS1
R/W
1
100%
150%
200%
CLKPS0
R/W
0
8006G–AVR–01/08
CLKPR